Datasheet

AD8842
REV. –5–
Table I. Serial Input Decode Table
Table II. Input Logic Control Truth Table
CLK LD PR Input Shift Register Operation
L L H No Operation
↑ L H Shift One Bit in from SDI (Pin 20), Shift One Bit* Out from SDO (Pin 18)
X L L All DAC Registers = 80
H
X Η H Load Serial Register Data into DAC(X) Register
X H X Serial Data Input Register Loading Disabled
*Data shifted into the SDI pin appears twelve clocks later at the SDO pin.
LSB
D0
D1 D2 D3 D4 D5 D6
MSB
D7
LSB
A0
A1 A2
MSB
A3
LAST
FIRST
A3 A2 A1 A0
ADDRESSDATA
MSB LSB
DAC UPDATED
NO OPERATION
DAC A
DAC B
DAC C
DAC D
DAC H
NO OPERATION
NO OPERATION
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
1
1
D7 D6 D5 D4 D3 D2 D1 D0
DAC OUTPUT VOLTAGE
V
OUT
= (D/128 –1) x V
IN
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
MSB
LSB
–V
IN
(1/128–1) x V
IN
(127/128–1) x V
IN
(128/128–1) x V
IN
= 0V; (PRESET VALUE)
(129/128–1) x V
IN
(254/128–1) x V
IN
(255/128–1) x V
IN
≈ V
IN
•
•
•
•
•
•
•
•
•
•
•
•
0
0
1
0
0
1
1
A