Datasheet

AD8842–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Units
STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H
Resolution N 8 Bits
Integral Nonlinearity Error INL ±0.2 ±1 LSB
Differential Nonlinearity DNL All Devices Monotonic ±0.4 ±1 LSB
Full-Scale Gain Error G
FSE
2 LSB
Output Offset V
BZE
PR = 0, Sets D = 80
H
525mV
Output Offset Drift TCV
BZ
PR = 0, Sets D = 80
H
5 µV/°C
VOLTAGE INPUTS—Applies to All Inputs V
IN
x
Input Voltage Range
1
IVR ±3 ±4V
Input Resistance R
IN
12 19 kΩ
Input Capacitance C
IN
9pF
DAC OUTPUTS—Applies to All Outputs V
OUT
x
Voltage Range
1
OVR R
L
= 10 kΩ±3±4V
Output Current I
OUT
∆V
OUT
< 1.5 LSB ±3mA
Capacitive Load C
L
No Oscillation 500 pF
DYNAMIC PERFORMANCE—Applies to All DACs
Full Power Gain Bandwidth
1
GBW V
IN
x = ±3 V
P
, R
L
= 2 kΩ, C
L
= 10 pF 10 50 kHz
Slew Rate Measured 10% to 90%
Positive SR+ ∆V
OUT
x = +5.5 V 0.5 1.0 V/µs
Negative SR– ∆V
OUT
x = –5.5 V 1.0 1.8 V/µs
Total Harmonic Distortion THD V
IN
x = 4 V p-p, D = FF
H
, f = 1 kHz, 0.01 %
f
LPF
= 80 kHz, R
L
= 1 kΩ
Spot Noise Voltage e
N
f = 1kHz, V
IN
= 0 V 78 nV/√Hz
Output Settling Time t
S
±1 LSB Error Band, D = 00
H
to FF
H
2.9 µs
D = FF
H
to 00
H
5.4 µs
Channel-to-Channel Crosstalk C
T
Measured Between Adjacent
Channels, f = 100 kHz 72 dB
Digital Feedthrough Q V
IN
x = 0 V, D = 0 to 255
10
5 nV-s
POWER SUPPLIES
Positive Supply Current I
DD
PR = 0 V 10 14 mA
Negative Supply Current I
SS
PR = 0 V 9 13 mA
Power Dissipation
2
P
DISS
95 135 mW
Power Supply Rejection PSRR
PR = 0 V, ∆V
DD
= ± 5% 0.0001 0.01 %/%
Power Supply Range PSR V
DD
, |V
SS
| 4.75 5.00 5.25 V
DIGITAL INPUTS
Logic High V
IH
2.4 V
Logic Low V
IL
0.8 V
Input Current I
L
±10 µA
Input Capacitance C
IL
7pF
Input Coding Offset Binary
DIGITAL OUTPUT
Logic High V
OH
I
OH
= –0.4 mA 3.5 V
Logic Low V
OL
I
OL
= 1.6 mA 0.4 V
TIMING SPECIFICATIONS
1
Input Clock Pulse Width t
CH
, t
CL
60 ns
Data Setup Time t
DS
40 ns
Data Hold Time t
DH
20 ns
CLK to SDO Propagation Delay t
PD
80 ns
DAC Register Load Pulse Width t
LD
70 ns
Preset Pulse Width t
PR
50 ns
Clock Edge to Load Time t
CKLD
30 ns
Load Edge to Next Clock Edge t
LDCK
60 ns
NOTES
1
Guaranteed by design, not subject to production test.
2
Calculated limit = 5 V × (I
DD
+ I
SS
).
Specifications subject to change without notice.
REV. –2–
(V
DD
= +5 V, V
SS
= –5 V, All V
IN
x = +3 V, T
A
= –40°C to +85°C, unless otherwise noted.)
A