Datasheet

AD8802/AD8804
REV. 0
–5–
100
0.0001
2.5
0.01
0.001
0.50
0.1
1.0
10
21.51
INPUT VOLTAGE – Volts
53 4.543.5
T
A
= +25°C
ALL DIGITAL INPUTS
TIED TOGETHER
SUPPLY CURRENT – mA
V
DD
= +5V
V
DD
= +3V
Figure 7. Supply Current vs. Logic Input Voltage
80
60
40
20
0
100 100k10k1k10
FREQUENCY – Hz
PSRR – dB
V
DD
= +5V
ALL OUTPUTS SET
TO MIDSCALE (80H)
Figure 8. Power Supply Rejection vs. Frequency
10
0%
100
90
0%
V
DD
= +5V
V
REF
= +5V
TIME – 5µs/DIV
4V
0V
5V
0V
OUT
CS
2V
5µs
6V
2V
5V
Figure 9. Large-Signal Settling Time
10
0%
100
90
OUTPUT1: OO
H
→ FF
H
TIME – 0.2µs/DIV
OUTPUT2 – 10mV/DIV
10mV
200ns
V
DD
= +5V
V
REF
= +5V
f = 1MHz
Figure 10. Adjacent Channel Clock Feedthrough
10
0%
100
90
OUTPUT1: 7F
H
→ 80
H
V
DD
= +5V
V
REF
= +5V
TIME – 1µs/DIV
OUT1
5mV/DIV
CS
5V/DIV
5mV 1µs
5V
Figure 11. Midscale Transition
HOURS OF OPERATION AT 150°C
0.01
–0.01
0
–0.005
0.005
0
600100 300 500
CHANGE IN ZERO-SCALE ERROR – LSB
V
DD
= +4.5V
V
REF
= +4.5V
SS = 176 PCS
V
REFL
= 0V
200 400
Figure 12. Zero-Scale Error Accelerated by Burn-In