Datasheet

Parameter Symbol Conditions Min Typ
1
Max Units
STATIC ACCURACY
Specifications apply to all DACs
Resolution N 8 Bits
Differential Nonlinearity Error DNL Guaranteed Monotonic –1 ±1/4 +1 LSB
Integral Nonlinearity Error INL –1.5 ±1/2 +1.5 LSB
Full-Scale Error G
FSE
–1 1/2 +1 LSB
Zero Code Error V
ZSE
–1 1/4 +1 LSB
DAC Output Resistance R
OUT
35 8 kΩ
Output Resistance Match ∆R/R
O
1.5 %
REFERENCE INPUT
Voltage Range
2
V
REFH
0V
DD
V
V
REFL
Pin Available on AD8804 Only 0 V
DD
V
REFH Input Resistance R
REFH
Digital Inputs = 55
H
, V
REFH
= V
DD
1.2 kΩ
REFL Input Resistance
3
R
REFL
Digital Inputs = 55
H
, V
REFL
= V
DD
1.2 kΩ
Reference Input Capacitance
3
C
REF0
Digital Inputs all Zeros 32 pF
C
REF1
Digital Inputs all Ones 32 pF
DIGITAL INPUTS
Logic High V
IH
V
DD
= +5 V 2.4 V
Logic Low V
IL
V
DD
= +5 V 0.8 V
Logic High V
IH
V
DD
= +3 V 2.1 V
Logic Low V
IL
V
DD
= +3 V 0.6 V
Input Current I
IL
V
IN
= 0 V or + 5 V ±1 µA
Input Capacitance
3
C
IL
5pF
POWER SUPPLIES
4
Power Supply Range V
DD
Range 2.7 5.5 V
Supply Current (CMOS) I
DD
V
IH
= V
DD
or V
IL
= 0 V 0.01 10 µA
Supply Current (TTL) I
DD
V
IH
= 2.4 V or V
IL
= 0.8 V, V
DD
= +5.5 V 1 4 mA
Shutdown Current I
REFH
SHDN = 0 0.2 10 µA
Power Dissipation P
DISS
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= +5.5 V 55 µW
Power Supply Sensitivity PSRR V
DD
= +5 V ± 10% 0.001 0.002 %/%
DYNAMIC PERFORMANCE
3
V
OUT
Settling Time t
S
±1/2 LSB Error Band 0.6 µs
Crosstalk CT Between Adjacent Outputs
5
50 dB
SWITCHING CHARACTERISTICS
3, 6
Input Clock Pulse Width t
CH
, t
CL
Clock Level High or Low 15 ns
Data Setup Time t
DS
5ns
Data Hold Time t
DH
5ns
CS Setup Time t
CSS
10 ns
CS High Pulse Width t
CSW
10 ns
Reset Pulse Width t
RS
90 ns
CLK Rise to
CS Rise Hold Time t
CSH
20 ns
CS Rise to Clock Rise Setup t
CS1
10 ns
NOTES
1
Typicals represent average readings at +25°C.
2
V
REFH
can be any value between GND and V
DD
, for the AD8804 V
REFL
can be any value between GND and V
DD
.
3
Guaranteed by design and not subject to production test.
4
Digital Input voltages V
IN
= 0 V or V
DD
for CMOS condition. DAC outputs unloaded. P
DISS
is calculated from (I
DD
× V
DD
).
5
Measured at a V
OUT
pin where an adjacent V
OUT
pin is making a full-scale voltage change (f = 100 kHz).
6
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of V
DD
) and timed from a voltage level of
1.6 V.
Specifications subject to change without notice.
AD8802/AD8804–SPECIFICATIONS
REV. 0
–2–
(V
DD
= +3 V 6 10% or +5 V 6 10%, V
REFH
= +V
DD
, V
REFL
= 0 V, –408C
≤T
A
≤ +858C unless otherwise noted)