Datasheet

REV. A
–8–
AD8801/AD8803
HOURS OF OPERATION AT 150°C
0.04
–0.04
0 600150 300 450
0
–0.02
0.02
V
DD
= +4.5V
V
REF
= +4.5V
SS = 162 PCS
x + 2σ
CHANGE IN FULL-SCALE ERROR – LSB
x
x – 2σ
Figure 19. Full-Scale Error Accelerated by Burn-In
HOURS OF OPERATION AT 150°C
1.0
INPUT RESISTANCE DRIFT – kΩ
–1.0
0 600150 300 450
0
–0.5
0.5
V
DD
= +4.5V
V
REF
= +4.5V
CODE = 55
H
SS = 162 PCS
x + 2σ
x
x – 2σ
Figure 20. REF Input Resistance Accelerated by Burn-In
AD8801/
AD8803
V
DD
DGND
10µF
0.1µF
+
+5V
Figure 22. Recommended Supply Bypassing for the
AD8801/AD8803
Buffering the AD8801/AD8803 Output
In many cases, the nominal 5 kΩ output impedance of the
AD8801/AD8803 is sufficient to drive succeeding circuitry. If a
lower output impedance is required, an external amplifier can
be added. Several examples are shown in Figure 23. One ampli-
fier of an OP291 is used as a simple buffer to reduce the output
resistance of DAC A. The OP291 was chosen primarily for its
rail-to-rail input and output operation, but it also offers opera-
tion to less than 3 V, low offset voltage, and low supply current.
The next two DACs, B and C, are configured in a summing ar-
rangement where DAC C provides the coarse output voltage
setting and DAC B can be used for fine adjustment. The inser-
tion of R1 in series with DAC B attenuates its contribution to
the voltage sum node at the DAC C output.
APPLICATIONS
Supply Bypassing
Precision analog products, such as the AD8801/AD8803, re-
quire a well filtered power source. Since the AD8801/AD8803
operate from a single +3 V to +5 V supply, it seems convenient
to simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches hundred of millivolts in amplitude due to
wiring resistances and inductances.
If possible, the AD8801/AD8803 should be powered directly
from the system power supply. This arrangement, shown in Fig-
ure 21, will isolate the analog section from the logic switching
transients. Even if a separate power supply trace is not available,
however, generous supply bypassing will reduce supply-line in-
duced errors. Local supply bypassing consisting of a 10 µF tan-
talum electrolytic in parallel with a 0.1 µF ceramic capacitor is
recommended (Figure 22).
TTL/CMOS
LOGIC
CIRCUITS
+5V
POWER SUPPLY
10µF
TANT
0.1µF
AD8801/
AD8803
+
Figure 21. Use Separate Traces to Reduce Power Supply
Noise