Datasheet
AD8613/AD8617/AD8619
Rev. E | Page 14 of 16
100708-A
*
COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
1.60 BSC
2.80 BSC
1.90
BSC
0.95 BSC
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
0.50
0.30
0.10 MAX
*
1.00 MAX
*
0.90 MAX
0.70 MIN
2.90 BSC
54
123
SEATING
PLANE
Figure 43. 5-Lead Thin Small Outline Transistor Package [TSOT-23]
(UJ-5)
Dimensions shown in millimeters
051909-A
1
EXPOSED
PAD
BOTTOM VIEW
0.50
BSC
PIN 1
INDICATOR
0.50
0.40
0.30
TOP VIEW
12° MAX
0.70 MAX
0.65TYP
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
0.20 REF
2.23
2.13
2.03
4
1.60
1.50
1.40
3.25
3.00 SQ
2.75
2.95
2.75 SQ
2.55
5
8
PIN 1
INDICATOR
SEATING
PLANE
0.30
0.23
0.18
0.60 MAX
0.60 MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 44. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-9)
Dimensions shown in millimeters