Datasheet

AD8557
Rev. C | Page 3 of 24
SPECIFICATIONS
VDD = 5.0 V, VSS = 0.0 V, V
CM
= 2.5 V, VOUT = 2.5 V, gain = 28, T
A
= −40°C to +125°C, unless otherwise specified.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT STAGE
Input Offset Voltage V
OS
2 12 μV
Input Offset Voltage Drift T
C
V
OS
27 65 nV/°C
Input Bias Current I
B
10 18 25 nA
Input Offset Current I
OS
1 4 nA
Input Voltage Range 0.6 3.8 V
Common-Mode Rejection Ratio CMRR V
CM
= 0.9 V to 3.6 V, A
V
= 28 75 85 dB
V
CM
= 0.9 V to 3.6 V, A
V
= 1300 96 112 dB
Linearity VOUT = 0.2 V to 3.4 V 20 ppm
VOUT = 0.2 V to 4.8 V 1000 ppm
Differential Gain Accuracy Second stage gain = 10 to 70 1.6 %
Differential Gain Accuracy Second stage gain = 100 to 250 2.5 %
Differential Gain Temperature Coefficient Second stage gain = 10 to 250 15 40 ppm/°C
DAC
Accuracy Offset codes = 8 to 248 0.7 0.8 %
Ratiometricity Offset codes = 8 to 248 50 ppm
Output Offset Offset codes = 8 to 248 5 35 mV
Temperature Coefficient 20 80 ppm FS/°C
VCLAMP
Clamp Input Bias Current ICLAMP 1.25 V to 5.0 V 200 nA
Clamp Input Voltage Range 1.25 5.0 V
OUTPUT STAGE
Short-Circuit Current I
SC
Source −45 −25 mA
I
SC
Sink 40 55 mA
Output Voltage, Low V
OL
R
L
= 10 kΩ to 5 V 30 mV
Output Voltage, High V
OH
R
L
= 10 kΩ to 0 V 4.94 V
POWER SUPPLY
Supply Current I
SY
VPOS = VNEG = 2.5 V,
VDAC code = 128, VOUT = 2.5 V
1.8 mA
Power Supply Rejection Ratio PSRR VDD = 2.7 V to 5.5 V 105 125 dB
DYNAMIC PERFORMANCE
Gain Bandwidth Product GBP First gain stage, T
A
= 25°C 2 MHz
Second gain stage, T
A
= 25°C 8 MHz
Settling Time t
s
To 0.1%, 4 V output step 8 µs
NOISE PERFORMANCE
Input Referred Noise f = 1 kHz, T
A
= 25°C 32 nV/√Hz
Low Frequency Noise e
n
p-p f = 0.1 Hz to 10 Hz, T
A
= 25°C 0.5 µV p-p
Total Harmonic Distortion THD V
IN
= 16.75 mV rms, f = 1 kHz,
T
A
= 25°C
−100 dB
DIGITAL INTERFACE
Input Current 2 µA
DIGIN Pulse Width to Load 0 tw
0
T
A
= 25°C 0.05 10 µs
DIGIN Pulse Width to Load 1 tw
1
T
A
= 25°C 50 µs
Time Between Pulses at DIGIN tw
s
T
A
= 25°C 10 µs
DIGIN Low T
A
= 25°C 0.2 × VDD V
DIGIN High T
A
= 25°C 0.8 × VDD V
DIGOUT Logic 0 T
A
= 25°C 0.2 × VDD V
DIGOUT Logic 1 T
A
= 25°C 0.8 × VDD V