Datasheet

AD8556
Rev. A | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
0
5448-002
VDD 1
FILT/DIGOUT 2
DIGIN
3
VNEG
4
VSS 8
VOUT 7
VCLAMP
6
VPOS
5
AD8556
TOP VIEW
(Not to Scale)
Figure 2. 8-Lead SOIC_N Pin Configuration
05448-003
12
11
10
9
NC
VCLAMP
NC
VOUT
1 NC
2
3
5
NC
VNEG
NC
VPOS
6 7 8
4 DIGIN
NC
FILT/DIGOUT
16 15 14 13
AD8556
TOP VIEW
PIN 1
INDICATOR
AVDD DVDD AVSS DVSS
NC = NO CONNECT
Figure 3.16-Lead LFCSP_VQ Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
SOIC_N LFCSP_VQ
Mnemonic Description
1 VDD Positive Supply Voltage.
2 2 FILT/DIGOUT
Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between
FILT and VDD or VSS implements a low-pass filtering function. In read mode, this pin
functions as a digital output.
3 4 DIGIN Digital Input.
4 6 VNEG Negative Amplifier Input (Inverting Input).
5 8 VPOS Positive Amplifier Input (Noninverting Input).
6 10 VCLAMP Set Clamp Voltage at Output.
7 12 VOUT
Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin.
In read mode, VOUT is a buffered digital output.
8 VSS Negative Supply Voltage.
13, 14 DVSS, AVSS Negative Supply Voltage.
15, 16 DVDD, AVDD Positive Supply Voltage.
1, 3, 5, 7, 9, 11 NC Do Not Connect.