Datasheet

AD8556
Rev. A | Page 16 of 28
THEORY OF OPERATION
A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the
differential amplifier. A1 and A2 are auto-zeroed op amps that
minimize input offset errors. P1 and P2 are digital potentiometers,
guaranteed to be monotonic. Programming P1 and P2 allows
the first stage gain to be varied from 4.0 to 6.4 with 7-bit
resolution (see
Tabl e 5 and Equation 1), giving a fine gain
adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each
have a similar temperature coefficient; therefore, the first stage
gain temperature coefficient is lower than 100 ppm/°C.
⎟
⎠
⎞
⎜
⎝
⎛
⎟
⎠
⎞
⎜
⎝
⎛
×≈
127
4
6.4
4
Code
GAIN1 (1)
A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of
the differential amplifier. A3 is also an auto-zeroed op amp that
minimizes input offset errors. P3 and P4 are digital potentiometers
that allow the second stage gain to be varied from 17.5 to 200 in
eight steps (see
Tabl e 6). R4, R5, R6, R7, P3, and P4 each have a
similar temperature coefficient; therefore, the second stage gain
temperature coefficient is lower than 100 ppm/°C.
RF together with an external capacitor, connected between
FILT/DIGOUT and VSS or VDD, form a low-pass filter. The
filtered signal is buffered by A4 to give a low impedance output
at VOUT. RF is nominally 18 kΩ, allowing an 880 Hz low-pass
filter to be implemented by connecting a 10 nF external capacitor
between FILT/DIGOUT and VSS or between FILT/DIGOUT
and VDD. If low-pass filtering is not needed, the FILT/DIGOUT
pin must be left floating.
A5 implements a voltage buffer that provides the positive supply
to A4, the amplifier output buffer. Its function is to limit VOUT
to a maximum value, useful for driving ADCs operating on
supply voltages lower than VDD. The input to A5, VCLAMP,
has a very high input resistance. It should be connected to a
known voltage and not left floating. However, the high input
impedance allows the clamp voltage to be set using a high
impedance source, such as a potential divider. If the maximum
value of VOUT does not need to be limited, VCLAMP should
be connected to VDD.
A4 implements a rail-to-rail input and output unity-gain
voltage buffer. The output stage of A4 is supplied from a
buffered version of VCLAMP instead of VDD, allowing the
positive swing to be limited. The maximum output current is
limited between 5 mA to 10 mA.
An 8-bit DAC is used to generate a variable offset for the
amplifier output. This DAC is guaranteed to be monotonic.
To preserve the ratiometric nature of the input signal, the DAC
references are driven from VSS and VDD, and the DAC output
can swing from VSS (Code 0) to VDD (Code 255). The 8-bit
resolution is equivalent to 0.39% of the difference between
VDD and VSS, for example, 19.5 mV with a 5 V supply. The
DAC output voltage (VDAC) is given approximately by
()
VSSVSSVDD
Code
VDAC +−
⎟
⎠
⎞
⎜
⎝
⎛
+
≈
256
0.5
(2)
where the temperature coefficient of VDAC is lower than
200 ppm/°C.
The amplifier output voltage (VOUT) is given by
VOUT = GAIN (VPOS − VNEG) + VDAC (3)
where GAIN is the product of the first and second stage gains.
A3
A2
A4
A5
VDD
VDD
DAC
VSS
VSS
VDD
VSS
VDD
V
DD
VSS
VCLAMP
VPOS
VSS
FILT/
DIGOUT
VOUT
A1
VDD
VSS
VNEG
R1
R3
R2
R5 R7
P4
R4
R6
RF
P3
P2
P1
05448-001
Figure 47. Functional Schematic