Digitally Programmable Sensor Signal Amplifier with EMI Filters AD8556 FEATURES APPLICATIONS EMI filters at input pins Specified from −40°C to +140°C Low offset voltage: 10 μV maximum Low input offset voltage drift: 65 nV/°C maximum High CMRR: 94 dB minimum Digitally programmable gain and output offset voltage Programmable output clamp voltage Open and short wire fault detection Low-pass filtering Single-wire serial interface Stable with any capacitive load SOIC_N and LFCSP_VQ packages 4.5 V to 5.
AD8556 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications....................................................................................... 1 Theory of Operation ...................................................................... 16 Functional Block Diagram ..............................................................
AD8556 GENERAL DESCRIPTION The AD8556 is a zero-drift, sensor signal amplifier with digitally programmable gain and output offset. Designed to easily and accurately convert variable pressure sensor and strain bridge outputs to a well-defined output voltage range, the AD8556 accurately amplifies many other differential or single-ended sensor outputs. The AD8556 uses the Analog Devices, Inc.
AD8556 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, −40°C ≤ TA ≤ +140°C, unless otherwise specified. Table 1.
AD8556 Parameter DYNAMIC PERFORMANCE Gain Bandwidth Product Symbol Conditions GBP Output Buffer Slew Rate Settling Time NOISE PERFORMANCE Input Referred Noise Low Frequency Noise Total Harmonic Distortion SR ts First gain stage, TA = 25°C Second gain stage, TA = 25°C Output buffer stage, TA = 25°C AV = 70, RL = 10 kΩ, CL = 100 pF, TA = 25°C To 0.1%, AV = 70, 4 V output step, TA = 25°C 2 8 1.5 1.2 8 MHz MHz MHz V/μs μs TA = 25°C, f = 1 kHz f = 0.1 Hz to 10 Hz, TA = 25°C VIN = 16.
AD8556 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Input Voltage Differential Input Voltage 1 Output Short-Circuit Duration to VSS or VDD Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature 1 Rating 6V VSS − 0.3 V to VDD + 0.3 V ±5.0 V Indefinite −65°C to +150°C −40°C to +150°C −65°C to +150°C 300°C Differential input voltage is limited to ±5.0 V or ± the supply voltage, whichever is less.
AD8556 TOP VIEW (Not to Scale) VNEG 4 8 VSS 7 VOUT 6 VCLAMP 5 VPOS 14 AVSS 13 DVSS VPOS 8 DIGIN 3 AD8556 05448-002 VDD 1 FILT/DIGOUT 2 TOP VIEW NC 5 DIGIN 4 AD8556 VNEG 6 NC 7 NC 3 PIN 1 INDICATOR NC = NO CONNECT 12 VOUT 11 NC 10 VCLAMP 9 NC 05448-003 NC 1 FILT/DIGOUT 2 15 DVDD 16 AVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3.16-Lead LFCSP_VQ Pin Configuration Figure 2. 8-Lead SOIC_N Pin Configuration Table 4.
AD8556 TYPICAL PERFORMANCE CHARACTERISTICS 25 N: 363 MEAN: –0.389938 SD: 1.65684 100 20 60 40 15 10 5 20 –5 0 5 0 05448-004 0 –10 10 VOS 5V (µV) 0 10 Figure 4. Input Offset Voltage Distribution 2.0 MORE VSY = 5V 1.9 BUFFER OFFSET VOLTAGE (mV) 1.0 0.5 0 VOSi (µV) 40 Figure 7. TCVOS at VSY = 5 V VSY = 5V TA = 25°C 1.5 20 30 TCVOS (nV/°C) 05448-007 NUMBER OF AMPLIFIERS 80 HITS VSY = 5V –0.5 –1.0 –1.5 –2.0 1.7 VOUT = 0.3V 1.5 1.3 VOUT = 4.7V 1.1 0.9 0.7 2.0 2.
AD8556 100 1000 VSY = 5V TA = 25°C IB– +125°C 0 1 2 3 4 5 6 VCM (V) +25°C –40°C 100 10 0 1 5 6 Figure 13. VCLAMP Current over Temperature at VS = 5 V vs. VCLAMP Voltage Figure 10. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage 3.0 0.8 VSY = 5V 0.6 TA = 25°C 2.5 0.5 0.3 SUPPLY CURRENT (mA) INPUT OFFSET CURRENT (nA) 2 3 4 VCLAMP VOLTAGE (V) 05448-014 VCLAMP CURRENT (nA) 10 05448-011 IB (nA) IB+ 1 VSY = 5V 0.2 0 –0.2 –0.3 –0.5 2.0 1.5 1.0 0.
AD8556 VSY = ±2.5V GAIN = 70 80 1k 10k FREQUENCY (Hz) 100k 1M 40 30 20 10 0 Figure 16. CMRR vs. Frequency 5 FREQUENCY (kHz) Figure 19. Voltage Noise Density vs. Frequency (0 Hz to 10 kHz) VSY = ±2.5V GAIN = 1280 VSY = ±2.5V GAIN = 70 VOLTAGE NOISE DENSITY (nV/√Hz) CMRR (dB) 120 80 1k 10k FREQUENCY (Hz) 100k 1M 05448-018 40 0 100 30 25 20 15 10 5 250 FREQUENCY (kHz) 500 Figure 20. Voltage Noise Density vs. Frequency (0 Hz to 500 kHz) VSY = 5V 145 VSY = ±2.5V GAIN = 1000 0.
AD8556 VSY = ±2.5V VSY = ±2.5V GAIN = 70 0.6 8 4 0.2 GAIN (dB) NOISE (µV) 0.4 0 0 –0.2 –4 –0.4 05448-023 TIME (1s/DIV) 1k 60 VSY = ±2.5V CL = 40pF RS OVERSHOOT (%) 40 GAIN = 70 20 0 RS = 0Ω CL OUTPUT BUFFER 30 RS = 10Ω 20 RS = 50Ω RS = 20Ω 10k 100k FREQUENCY (Hz) 1M RS = 100Ω 0 0.1 1 10 LOAD CAPACITANCE (nF) 100 05448-027 10 05448-024 Figure 26. Output Buffer Positive Overshoot 60 VSY = ±2.5V VSY = ±2.
AD8556 VSY = ±2.5V 6 SOURCE 0.100 VOLTAGE (1V/DIV) VDD – OUTPUT VOLTAGE (V) 1.000 SINK 0.010 SUPPLY VOLTAGE 5 4 3 2 1 10.0 05448-032 0.10 1.00 LOAD CURRENT (mA) VOUT 0 05448-029 0.001 0.01 TIME (100µs/DIV) Figure 31. Power-On Response at 125°C Figure 28. Output Voltage to Supply Rail vs.
AD8556 140 VSY = 2.7V TO 2.5V T VSY = ±2.5V GAIN = 70 CL = 100pF 120 80 VOUT (1V/DIV) PSRR (dB) 100 60 40 2 1 FREQUENCY (kHz) 10 100 TIME (10µs/DIV) Figure 34. PSRR vs. Frequency Figure 37. Large Signal Response at CL = 100 pF T VOUT (1V/DIV) VSY = ±2.5V GAIN = 70 CL = 0.1µF FIN = 10kHz 2 TIME (100µs/DIV) TIME (10µs/DIV) Figure 35. Small Signal Response at CL = 0.1 μF and FIN = 10 kHz Figure 38. Large Signal Response at CL = 0.05 μF 1k T VSY = ±2.5V GAIN = 70 CL = 0.
AD8556 0V 1 VIN 0V 1 VIN 0V 2 VOUT VOUT CH2 2.00V M 1.00µs A CH1 –21.0mV CH1 10.0mV Figure 40. Negative Overload Recovery (Gain = 70) CH2 2.00V M 4.00µs A CH1 05448-044 CH1 50.0mV 05448-041 0V 2 8.40mV Figure 43. Positive Overload Recovery (Gain = 1280) VIN 1 GAIN = 70 OFFSET = 128 VSY = ±2.5V +V 0V 1 4V pp VOUT 20.5Ω 4 294Ω 5 0.1µF 1 6 7 DUT 8 0V 2 0.1µF –V 1kΩ CH2 2.00V M 1.00µs A CH1 57.0mV 10kΩ OUT 2 CH1 2.00mV CH2 2.00mV M 1.00µs A CH1 40.
AD8556 1.00 VSY = ±2.5V 0.50 0.10 0.05 0.02 0.01 20 50 100 200 500 1k 2k FREQUENCY (Hz) 5k 10k 20k 05448-047 THD (%) 0.20 Figure 46. THD vs. Frequency Rev.
AD8556 THEORY OF OPERATION ⎛ Code ⎞ ⎜ ⎟ 127 ⎠ 6.4 ⎞ ⎝ GAIN1 ≈ 4 × ⎛⎜ ⎟ ⎝ 4 ⎠ (1) A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the differential amplifier. A3 is also an auto-zeroed op amp that minimizes input offset errors. P3 and P4 are digital potentiometers that allow the second stage gain to be varied from 17.5 to 200 in eight steps (see Table 6).
AD8556 GAIN VALUES Table 5. First Stage Gain vs. First Stage Gain Code First Stage Gain Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 First Stage Gain 4.000 4.015 4.030 4.045 4.060 4.075 4.090 4.105 4.120 4.135 4.151 4.166 4.182 4.197 4.213 4.228 4.244 4.260 4.276 4.291 4.307 4.323 4.339 4.355 4.372 4.388 4.404 4.420 4.437 4.453 4.470 4.
AD8556 OPEN WIRE FAULT DETECTION The inputs to A1 and A2, VNEG and VPOS, each have a comparator to detect whether VNEG or VPOS exceeds a threshold voltage, nominally VDD − 2.0 V. If (VNEG > VDD − 2.0 V) or (VPOS > VDD − 2.0 V), VOUT is clamped to VSS. The output current limit circuit is disabled in this mode, but the maximum sink current is approximately 10 mA when VDD = 5 V. The inputs to A1 and A2, VNEG and VPOS, are also pulled up to VDD by currents IP1 and IP2.
AD8556 tW1 tWS tWS tWS tW0 tW1 tW0 tW0 tWS tWS tW1 CODE 0 1 0 0 1 1 05448-049 WAVEFORM Figure 49. Timing Diagram for Code 010011 Table 9. Timing Specifications Timing Parameter tw0 tw1 tws Description Pulse width for loading 0 into shift register Pulse width for loading 1 into shift register Width between pulses Specification Between 50 ns and 10 μs ≥50 μs ≥10 μs Table 10. 38-Bit Serial Word Format Field No.
AD8556 Initial State Initially, all the polysilicon fuses are intact. Each parameter has the value 0 assigned (see Table 11). Table 11. Initial State Before Programming Second Stage Gain Code = 0 First stage gain code = 0 Output offset code = 0 Master fuse = 0 Second Stage Gain = 17.5 First stage gain = 4.0 Output offset = VSS Master fuse not blown At least 10 μF (tantalum type) of decoupling capacitance is needed across the power pins of the device during programming.
AD8556 Parity Error Detection The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to VC7) is fed to an 18-input exclusive-OR gate (Cell EOR18). The output of Cell EOR18 is the DAT_SUM signal. If there is an even number of 1s in the 18-bit word, DAT_SUM = 0; and if there is an odd number of 1s in the 18-bit word, DAT_SUM = 1. See Table 12 for examples.
AD8556 Read Mode The values stored by the polysilicon fuses can be sent to the FILT/DIGOUT pin to verify correct programming. Normally, the FILT/DIGOUT pin is only connected to the second gain stage output via RF. During read mode, however, the FILT/DIGOUT pin is also connected to the output of a shift register to allow the polysilicon fuse contents to be read. Because VOUT is a buffered version of FILT/DIGOUT, VOUT also outputs a digital signal during read mode.
AD8556 3. 4. 5. Important: Once a programming attempt is made for any fuse, there should be no further attempt to blow that fuse. If a fuse does not program to the expected state, discard the unit. The expected incidence rate of attempted but unblown fuses is very small when following the proper programming procedure and conditions. Set VSS to 0 V and VDD to 5.25 V (±0.25 V).
AD8556 EMI/RFI PERFORMANCE Real-world applications must work with ever increasing radio/magnetic frequency interference (RFI and EMI). In situations where signal strength is low and transmission lines are long, instrumentation amplifiers, such as the AD8556, are needed to extract weak, small differential signals riding on common-mode noise and interference. Additionally, wires and PCB traces act as antennas and pick up high frequency EMI signals. The longer the wire, the larger the voltage it picks up.
AD8556 To show the benefits that the AD8556 brings to new applications where EMI/RFI signals are present, a part was programmed with a gain of 70 and a dc offset of 2.5 V to produce a VOUT of 0 V. A test circuit like that shown in Figure 52 was used. Figure 52 simulates the presence of a noisy common-mode signal, and Figure 53 shows the response dc values at VOUT. +2.
AD8556 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 1 5 6.20 (0.2440) 4 5.80 (0.2284) 1.27 (0.0500) BSC 0.50 (0.0196) × 45° 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.
AD8556 NOTES Rev.
AD8556 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05448-0-12/07(A) Rev.
