Datasheet

AD8522–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution
1
N 12 Bits
Relative Accuracy INL -1.5 ±0.5 +1.5 LSB
Differential Nonlinearity DNL Monotonic -1 ±0.5 +1 LSB
Zero-Scale Error V
ZSE
Data = 000
H
+0.5 +3 mV
Full-Scale Voltage
2
V
FS
Data = FFF
H
4.079 4.095 4.111 Volts
Full-Scale Tempco
2, 3
TCV
FS
±15 ppm/°C
MATCHING PERFORMANCE
Linearity Matching Error ∆V
FS
A/B ±1 LSB
ANALOG OUTPUT
Output Current I
OUT
Data = 800
H
, ∆V
OUT
≤ 3 LSB ±5mA
Load Regulation at Half-Scale LD
REG
R
L
= 402 Ω to ∞, Data = 800
H
1 3 LSB
Capacitive Load
3
C
L
No Oscillation 500 pF
REFERENCE OUTPUT
Output Voltage V
REF
2.484 2.500 2.516 V
Output Source Current
4
I
REF
∆V
REF
< 18 mV 5 mA
Line Rejection LN
REJ
0.025 0.08 %/V
Load Regulation LD
REG
I
REF
= 0 to 5 mA, Data = 800
H
0.025 0.1 %/mA
LOGIC INPUTS & OUTPUTS
Logic Input Low Voltage V
IL
0.8 V
Logic Input High Voltage V
IH
2.4 V
Input Leakage Current I
IL
10 µA
Input Capacitance
3
C
IL
10 pF
Logic Output Voltage Low V
OL
I
OL
= 1.6 mA 0.4 V
Logic Output Voltage High V
OH
I
OH
= 400 µA 3.5 V
TIMING SPECIFICATIONS
3, 5
Clock Width High t
CH
35 ns
Clock Width Low t
CL
35 ns
Load Pulse Width t
LDW
25 ns
Data Setup t
DS
10 ns
Data Hold t
DH
20 ns
Clear Pulse Width t
CLRW
20 ns
Load Setup t
LD1
10 ns
Load Hold t
LD2
10 ns
Select t
CSS
30 ns
Deselect t
CSH
30 ns
Clock to SDO Propagation Delay t
PD
20 45 80 ns
AC CHARACTERISTICS
3, 5
Voltage Output Settling Time
6
t
S
To ±1 LSB of Final Value 16 µs
Crosstalk C
T
Signal Measured at DAC Output,
While Changing Opposite
LDA/B 38 dB
DAC Glitch Q Half-Scale Transition 13 nV s
Digital Feedthrough D
FT
Signal Measured at DAC Output,
While Changing Data Without LDA/B 2 nV s
SUPPLY CHARACTERISTICS
Positive Supply Current I
DD
V
DD
= 5.5 V, V
IH
= 2.4 V or V
IL
= 0.8 V 3 5 mA
V
DD
= 5 V, V
IL
= 0 V 1 2 mA
Power Dissipation
7
P
DISS
V
DD
= 5 V, V
IH
= 2.4 V or V
IL
= 0.8 V 15 25 mW
V
DD
= 5 V, V
IL
= 0 V 5 10 mW
Power Supply Sensitivity PSS ∆V
DD
= ±5% 0.002 0.004 %/%
NOTES
1
1 LSB = 1 mV for 0 V to +4.095 V output range.
2
Includes internal voltage reference error.
3
These parameters are guaranteed by design and not subject to production testing.
4
Very little sink current is available at the V
REF
pin. Use external buffer if setting up a virtual ground.
5
All input control signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.
7
Power Dissipation is calculated I
DD
× 5 V.
Specifications subject to change without notice.
(@ V
DD
= +5.0 V 6 10%, R
L
= No Load, –408C ≤ T
A
≤ +858C, both DACs tested, unless
otherwise noted)
REV. A
–2–