Datasheet

AD844
Rev. F | Page 16 of 20
DC ERROR CALCULATION
Figure 37 shows a model of the dc error and noise sources for
the AD844. The inverting input bias current, I
BN
, flows in the
feedback resistor. I
BP
, the noninverting input bias current, flows
in the resistance at Pin 3 (R
P
), and the resulting voltage (plus
any offset voltage) appears at the inverting input. The total
error, V
O
, at the output is:
()
R1I
R2
R1
RIVRIV
BNINBN
OS
PBP
O
+
⎟
⎠
⎞
⎜
⎝
⎛
+++= 1
Because I
BN
and I
BP
are unrelated both in sign and magnitude,
inserting a resistor in series with the noninverting input does
not necessarily reduce dc error and may actually increase it.
R2
V
N
I
NN
I
NP
R
P
R1
I
BP
I
BN
V
OS
AD844
R
IN
00897-037
Figure 37. Offset Voltage and Noise Model for the AD844
NOISE
Noise sources can be modeled in a manner similar to the dc bias
currents, but the noise sources are I
NN
, I
NP
, V
N
, and the amplifier
induced noise at the output, V
ON
, is:
()()()
2
2
2
2
1 R1I
R2
R1
VRIV
NNNPNP
ON
+
⎟
⎠
⎞
⎜
⎝
⎛
++=
Overall noise can be reduced by keeping all resistor values to a
minimum. With typical numbers, R1 = R2 = 1 kΩ, R
P
= 0 Ω,
V
N
= 2 nV/√Hz, I
NP
= 10 pA/√Hz, I
NN
= 12 pA/√Hz, and V
ON
calculates to 12 nV/√Hz. The current noise is dominant in this
case, because it is in most low gain applications.
VIDEO CABLE DRIVER USING ±5 V SUPPLIES
The AD844 can be used to drive low impedance cables. Using
±5 V supplies, a 100 Ω load can be driven to ±2.5 V with low
distortion. Figure 38 shows an illustrative application that
provides a noninverting gain of +2, allowing the cable to be
reverse-terminated while delivering an overall gain of +1 to the
load. The −3 dB bandwidth of this circuit is typically 30 MHz.
Figure 39 shows a differential gain and phase test setup. In video
applications, differential-phase and differential-gain characteris-
tics are often important. Figure 40 shows the variation in phase as
the load voltage varies. Figure 41 shows the gain variation.
V
IN
50Ω
50Ω
R
L
50Ω
300Ω
300Ω
3
2
+5
V
–5V
7
6
4
2.2µF
2.2µF
Z
O
= 50Ω
V
OUT
0
0897-038
Figure 38. The AD844 as a Cable Driver
HP8753A
NETWORK
ANALYZER
HP11850C
SPLITTER
CIRCUIT
UNDER
TEST
HP3314A
STAIRCASE
GENERATOR
V
OUT
V
IN
V
IN
OUT
OUT
OUT
INRF OUT
RF IN
EXT
TRIG
SYNC OUT
50Ω
(TERMINATOR)
OUT
470Ω
0
0897-039
Figure 39. Differential Gain/Phase Test Setup
V
OUT
(IRE)
DIFFERENTIAL PHASE (Degrees)
0.3
0.2
–0.3
90180
36 54 72
0.1
0
–0.1
–0.2
IRE = 7.14mV
00897-040
Figure 40. Differential Phase for the Circuit of Figure 38
V
OUT
(IRE)
DIFFERENTIAL GAIN (%)
0.06
0.04
–0.06
018 936 54 72
0.02
0
–0.02
–0.04
0
IRE = 7.14mV
00897-041
Figure 41. Differential Gain for the Circuit of Figure 38