Datasheet

Data Sheet AD8432
Rev. C | Page 21 of 32
APPLICATIONS INFORMATION
The AD8432 LNA provides precision gain and ultralow noise
performance with minimal external components. Because it is
a high performance part, care must be taken to ensure that it is
configured optimally to attain the best performance and dynamic
range for the system.
TYPICAL SETUP
The internal bias circuitry of the AD8432 sets the input bias
voltage at 3.25 V and the output bias voltage at 2.5 V. It is important
to ac couple the inputs through a capacitor to maintain the internal
dc bias levels. When active input termination is used (R
FB
), a
decoupling capacitor (C
FB
) is required to isolate the input and
output bias voltages of the LNA. A typical value for C
FB
is 0.1 µF, but
a smaller value capacitor is more appropriate at higher frequencies.
The unterminated input impedance of the AD8432 is 6.2 kΩ.
Any input resistance between 50 Ω and 6.2 kΩ can be synthesized
using active impedance matching.
At the lowest gain (12.04 dB), the gain response exhibits some
peaking at higher frequencies. A resistor-capacitor shunt net-
work (RC) at the input (see RSHx and CSHx in Figure 69) is
recommended to reduce gain peaking and enhance stability at
higher frequencies.
Table 7 shows the recommended values of R
FB
, C
SH
, and R
SH
for
all four gains and several input impedance combinations. The
values for the C
SH
and R
SH
network are determined empirically
and can be customized as needed to optimize performance. As
R
IN
increases, the value of C
SH
diminishes, and for higher input
impedance values, no capacitor may be required.
08341-040
R
L
R
SH2
15Ω
C
SH2
47pF
C
L
OUT2+
OUT2–
LNA2
0.1µF
0.1µF
0.1µF
0.1µF
FB
120nH
IN2
INL2
IND2
INH2
OPH2
OPL2
GMH2
GOH2
GOL2
GML2
R
FB2
C
FB2
0.1µF
C
FB1
0.1µF
AD8432
R
L
R
SH1
15Ω
C
SH1
47pF
C
L
OUT1+
OUT1–
LNA1
BIAS
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
FB
120nH
IN1
INL1
IND1
INH1
OPH1
OPL1
GMH1
GOH1
GOL1
GML1
FB
120nH
R
FB1
G = 12dB
COMM
VPS2
VPS1ENB
Figure 69. Typical AD8432 Setup, G = 12.04 dB