Datasheet

AD8400/AD8402/AD8403
Rev. E | Page 12 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
B1
1
GND
2
CS 3
SDI 4
A1 8
W1
7
V
DD
6
CLK
5
AD8400
TOP VIEW
(Not to Scale)
01092-006
Figure 6. AD8400 Pin Configuration
1
2
3
4
5
6
7
AD8402
B2
A2
W2
CS
SHDN
DGND
A
GND
14
13
12
11
10
9
8
A1
W1
V
DD
SDI
CLK
RS
B1
TOP VIEW
(Not to Scale)
01092-007
Figure 7. AD8402 Pin Configuration
A
GND2 1
B2
2
A2 3
W2 4
B1
24
A1 23
W1
22
AGND1 21
A
GND4
5
B4 6
A4
7
B3
20
A3 19
W3
18
W4 8
AGND3 17
DGND 9
V
DD
16
SHDN
10
RS 15
CS
11
CLK 14
SDI 12
SDO 13
AD8403
TOP VIEW
(Not to Scale)
01092-008
Figure 8. AD8403 Pin Configuration
Table 7. AD8400 Pin Function Descriptions
Pin No. Mnemonic Description
1 B1 Terminal B RDAC.
2 GND Ground.
3
CS
Chip Select Input, Active Low. When
CS
returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
4 SDI Serial Data Input.
5 CLK Serial Clock Input, Positive Edge Triggered.
6 V
DD
Positive Power Supply. Specified for operation at both 3 V and 5 V.
7 W1 Wiper RDAC, Addr = 00
2
.
8 A1 Terminal A RDAC.
Table 8. AD8402 Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND Analog Ground.
1
2 B2 Terminal B RDAC 2.
3 A2 Terminal A RDAC 2.
4 W2 Wiper RDAC 2, Addr = 01
2
.
5 DGND Digital Ground.
1
6
SHDN
Terminal A Open Circuit. Shutdown controls Variable Resistor 1 and Variable Resistor 2.
7
CS
Chip Select Input, Active Low. When
CS
returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
8 SDI Serial Data Input.
9 CLK Serial Clock Input, Positive Edge Triggered.
10
RS
Active Low Reset to Midscale. Sets RDAC registers to 80
H
.
11 V
DD
Positive Power Supply. Specified for operation at both 3 V and 5 V
12 W1 Wiper RDAC 1, Addr = 00
2
.
13 A1 Terminal A RDAC 1.
14 B1 Terminal B RDAC 1.
1
All AGND pins must be connected to DGND.