Datasheet

AD8400/AD8402/AD8403
Rev. E | Page 10 of 32
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
V
DD
= 3 V ± 10% or 5 V ± 10%, V
A
= V
DD
, V
B
= 0 V, −40°C ≤ T
A
≤ +125°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ
1
Max Unit
SWITCHING CHARACTERISTICS
2, 3
Input Clock Pulse Width t
CH
, t
CL
Clock level high or low 10 ns
Data Setup Time t
DS
5 ns
Data Hold Time t
DH
5 ns
CLK to SDO Propagation Delay
4
t
PD
R
L
= 1 kΩ to 5 V, C
L
≤ 20 pF 1 25 ns
CS
Setup Time
t
CSS
10 ns
CS
High Pulse Width
t
CSW
10 ns
Reset Pulse Width t
RS
50 ns
CLK Fall to
CS
Rise Hold Time
t
CSH
0 ns
CS
Rise to Clock Rise Setup
t
CS1
10 ns
1
Typicals represent average readings at 25°C and V
DD
= 5 V.
2
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
3
See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and
timed from a voltage level of 1.6 V. Switching characteristics are measured using V
DD
= 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
of 1 V/µs should be maintained.
4
Propagation delay depends on the value of V
DD
, R
L
, and C
L
(see the Applications section).
TIMING DIAGRAMS
DAC REGISTER LOAD
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
1
0
V
DD
0V
SDI
CLK
V
OUT
CS
01092-003
Figure 3. Timing Diagram
±1% ERROR BAND
±1%
t
CSH
t
CSS
t
DH
Ax OR DxAx OR Dx
t
PD_MIN
t
PD_MAX
A'x OR D'x A'x OR D'x
1
0
1
0
1
0
V
DD
0V
SDI
(DATA IN)
CLK
CS
V
OUT
1
0
SDO
(DATA OUT)
t
DS
t
CH
t
CS1
t
CL
t
S
t
CSW
01092-004
Figure 4. Detailed Timing Diagram
±1%
±1% ERROR BAND
1
0
V
DD
V
DD
/2
V
OUT
t
RS
t
S
RS
01092-005
Figure 5. Reset Timing Diagram