Datasheet

AD8376 Data Sheet
Rev. B | Page 18 of 24
LAYOUT CONSIDERATIONS
Each amplifier has two output pins for each polarity, and they
are oriented in an alternating fashion. When designing the
board, care should be taken to minimize the parasitic capaci-
tance due to the routing that connects the corresponding
outputs together. A good practice is to avoid any ground or
power plane under this routing region and under the chokes to
minimize the parasitic capacitance.
CHARACTERIZATION TEST CIRCUITS
Differential-to-Differential Characterization
The S-parameter characterization for the AD8376 was
performed using a dedicated differential input to differential
output characterization board. Figure 45 shows the layout of the
characterization board. The board was designed for optimum
impedance matching into a 75 Ω system. Because both the
input and output impedances of the AD8376 are 150 Ω differ-
entially, 75 Ω impedance runs were used to match 75 Ω network
analyzer port impedances. On-board 1 μH inductors were used
for output biasing, and the output board traces were designed
for minimum capacitance.
0.1µF
0.1µF
06725-050
L1
1µH
L2
1µH
0.1µF
0.1µF
+5V
5
A0 TO A4
AC
75Ω TRACES75Ω TRACES
75Ω
75Ω
75Ω
75Ω
AC
1/2
AD8376
Figure 43. Test Circuit for S-Parameters on Dedicated 75 Ω
Differential-to-Differential Board
0.1µF
0.1µF
TC3-1T
06725-051
T1
0.1µF
0.1µF
330Ω
330Ω
25Ω
25Ω
50Ω
+9V
5
A0 TO A4
50Ω
96Ω
96Ω
AC
1/2
AD8376
Figure 44. Test Circuit for Time Domain Measurements
06275-044
Figure 45. Differential-to-Differential Characterization Board
Circuit Side Layout
C1
0.1µF
C2
0.1µF
TC3-1T
06725-043
T1
L1
1µH
L2
1µH
C3
0.1µF
C4
0.1µF
R1
62Ω
R2
62Ω
R4
25Ω
R3
25Ω
ETC1-1-13
T2
50Ω
PAD LOSS = 11dB
+5V
5
A0 TO A4
50Ω
AC
1/2
AD8376
Figure 46. Test Circuit for Distortion, Gain, and Noise