Datasheet

AD8370 Data Sheet
Rev. B | Page 4 of 28
Parameter Conditions Min Typ Max Unit
140 MHz
Gain Flatness Within ±10 MHz of 140 MHz ±0.03 dB
Noise Figure 7.2 dB
Second Harmonic
1
V
OUT
= 2 V p-p −54 dBc
Third Harmonic
1
V
OUT
= 2 V p-p
−50
dBc
Output IP3 33 dBm
Output 1 dB Compression Point 17 dBm
190 MHz
Gain Flatness Within ±10 MHz of 240 MHz ±0.03 dB
Noise Figure 7.2 dB
Second Harmonic
1
V
OUT
= 2 V p-p −43 dBc
Third Harmonic
1
V
OUT
= 2 V p-p −43 dBc
Output IP3 33 dBm
Output 1 dB Compression Point 17 dBm
240 MHz
Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB
Noise Figure 7.4 dB
Second Harmonic
1
V
OUT
= 2 V p-p –28 dBc
Third Harmonic
1
V
OUT
= 2 V p-p –33 dBc
Output IP3 32 dBm
Output 1 dB Compression Point 17 dBm
380 MHz
Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB
Noise Figure 8.1 dB
Output IP3 27 dBm
Output 1 dB Compression Point 14 dBm
POWER-INTERFACE
Supply Voltage 3.0
2
5.5 V
Quiescent Current
3
PWUP High, GC = LG127, R
L
= ∞, 4 seconds after
power-on, thermal connection made to exposed
paddle under device
72.5 79 85.5 mA
vs. Temperature
4
−40°C ≤ T
A
≤ +85°C 105 mA
Total Supply Current PWUP High, V
OUT
= 1 V p-p, Z
L
= 100 Ω reactive,
GC = LG127 (includes load current)
82 mA
Power-Down Current
PWUP low
3.7
mA
vs. Temperature
4
−40°C ≤T
A
≤ +85°C
5
mA
POWER-UP INTERFACE Pin PWUP
Power-Up Threshold
4
Voltage to enable the device 1.8 V
Power-Down Threshold
4
Voltage to disable the device 0.8 V
PWUP Input Bias Current PWUP = 0 V 400 nA
GAIN CONTROL INTERFACE Pins CLCK, DATA, and LTCH
V
IH
4
Voltage for a logic high 1.8 V
V
IL
4
Voltage for a logic low 0.8 V
Input Bias Current 900 nA
1
Refer to Figure 22 for performance into a lighter load.
2
See the 3 V Operation section for more information.
3
Minimum and maximum specified limits for this parameter are guaranteed by production test.
4
Minimum or maximum specified limit for this parameter is a 6-sigma value and not guaranteed by production test.