Datasheet

REV. 0–4–
AD8369
Parameter Conditions Min Typ Max Unit
Frequency = 380 MHz
Voltage Gain 38.5 dB
Gain Flatness Within ± 20 MHz of 380 MHz ± 0.15 dB
Noise Figure 7.8 dB
Output IP3 f1 = 379.55 MHz, f2 = 380.45 MHz +8.5 dBV rms
+8.5 dBm
IMD
3
f1 = 379.55 MHz, f2 = 380.45 MHz,
V
OPHI
– V
OPLO
= 1 V p-p composite –47 dBc
Harmonic Distortion Second-Order, V
OPHI
– V
OPLO
= 1 V p-p –45 dBc
Third-Order, V
OPHI
– V
OPLO
= 1 V p-p –49 dBc
P1dB For ± 1 dB deviation from linear gain +0.5 dBV rms
+0.5 dBm
Specifications subject to change without notice.
SPECIFICATIONS (Continued)
TIMING SPECIFICATIONS
SERIAL PROGRAMMING TIMING REQUIREMENTS
(V
S
= 5 V, T = 25 ∞ C)
Parameter Typ Unit
Minimum Clock Pulsewidth (T
PW
)10ns
Minimum Clock Period (T
CK
)20ns
Minimum Setup Time Data vs. Clock (T
DS
)2ns
Minimum Setup Time Data Enable vs. Clock (T
ES
)2 ns
Minimum Hold Time Clock vs. Data Enable (T
EH
)2 ns
Minimum Hold Time Data vs. Clock (T
DH
)4ns
T
CK
T
PW
T
EH
T
ES
CLOCK
DISABLED
CLOCK
DISABLED
CLOCK
ENABLED
DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB
(NOT TO SCALE)
T
DH
T
DS
MSB MSB–1 MSB–2 LSB
CLOCK
(BIT 1)
DATA
(BIT 0)
DATA
ENABLE
(DENB)
Serial Programming Timing
PARALLEL PROGRAMMING TIMING REQUIREMENTS
(V
S
= 5 V, T = 25 ∞ C)
Parameter Typ Unit
Minimum Setup Time Data Enable vs. Data (T
ES
)2 ns
Minimum Hold Time Data Enable vs. Data (T
EH
)2 ns
Minimum Data Enable Width (T
PW
)4ns
MSB
(BIT3)
DATA IS LATCHED ON HIGH-TO-LOW
TRANSITION OF DENB
DENB
T
ES
T
EH
T
PW
LSB
(BIT0)
MSB–2
(BIT1)
MSB–1
(BIT2)
(NOT TO SCALE)
Parallel Programming Timing