Datasheet

REV. 0–2–
AD8369–SPECIFICATIONS
(V
S
= 5 V, T = 25ⴗC, R
S
= 200 ⍀, R
L
= 1000 ⍀, Frequency = 70 MHz, at maximum gain,
unless otherwise noted.)
Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION
Frequency Range 3 dB Bandwidth LF* 600 MHz
GAIN CONTROL INTERFACE
Voltage Gain Span 45 dB
Maximum Gain All bits high (1 1 1 1) 40 dB
Minimum Gain All bits low (0 0 0 0) –5 dB
Gain Step Size 3dB
Gain Step Accuracy
Over entire gain range, with respect to 3 dB step ± 0.05 dB
Gain Step Response Time Step = 3 dB, settling to 10% of final value 30 ns
INPUT STAGE
Input Resistance From INHI to INLO 200 W
From INHI to COMM, from INLO to COMM 100 W
Input Capacitance From INHI to INLO 0.1 pF
From INHI to COMM, from INLO to COMM 1.1 pF
Input Noise Spectral Density 2 nV/÷Hz
Input Common-Mode DC Voltage Measured at pin CMDC 1.7 V
Maximum Linear Input |V
INHI
– V
INLO
| at Minimum Gain 2.2 V
OUTPUT STAGE
Output Resistance From OPHI to OPLO 200 W
From OPHI to COMM, from OPLO to COMM 100 W
Output Capacitance From OPHI to OPLO 0.25 pF
From OPHI to COMM, from OPLO to COMM 1.5 pF
Common-Mode DC Voltage No input signal V
S
/2 V
Slew Rate Output step = 1 V 1200 V/ms
POWER INTERFACE
Supply Voltage 3.0 5.5 V
Quiescent Current PWUP high 37 42 mA
vs. Temperature –40∞C £ T
A
£ 85∞C52mA
Disable Current PWUP low 400 750 mA
vs. Temperature –40∞C £ T
A
£ 85∞C1mA
POWER UP INTERFACE Pin PWUP
Enable Threshold 1.0 V
Disable Threshold 2.2 V
Response Time Time delay following low to high transition 7 ms
on PWUP until output settles to within 10%
of final value
Input Bias Current PWUP = 5 V 160 mA
DIGITAL INTERFACE
Pins SENB, BIT0, BIT1, BIT2, BIT3,
and DENB
Low Condition 2.0 V
High Condition 3.0 V
Input Bias Current Low input 150 mA
Frequency = 10 MHz
Voltage Gain 40.5 dB
Gain Flatness Within ± 10 MHz of 10 MHz
+0.05* dB
Noise Figure 7.0 dB
Output IP3 f1 = 9.945 MHz, f2 = 10.550 MHz +22 dBV rms
+22 dBm
IMD
3
f1 = 9.945 MHz, f2 = 10.550 MHz
V
OPHI
– V
OPLO
= 1 V p-p composite –74 dBc
Harmonic Distortion Second-Order, V
OPHI
– V
OPLO
= 1 V p-p –72 dBc
Third-Order, V
OPHI
– V
OPLO
= 1 V p-p –71 dBc
P1dB For ± 1dB deviation from linear gain +3 dBV rms
+3 dBm
*The low frequency high-pass corner is determined by the capacitor on pin FILT, C
FILT
. See the Theory of Operation section for details.