Datasheet

REV. 0
AD8369
–15–
0.1␮F
R
L
0.1␮F
0.1␮F
R
L
0.1␮F
CONTROL INTERFACE
910111213141516
PWUP VPOS SENB FILT CMDC OPHI
INHI
COMM
INLO DENBCOMM BIT0 BIT1 BIT2 BIT3
AD8369
OPLO
0.1␮F
87654321
0.1␮F
0.1␮F
3V TO 5.5V
TC4-1W
50⍀ TX LINE
INⴙ
V
S
Figure 3. Basic Connections
BASIC CONNECTIONS
Figure 3 shows the minimum connections required for basic
operation of the AD8369. Supply voltages of between +3 V and
+5.5 V are permissible. The supply to the VPOS pin should be
decoupled with at least one low inductance surface-mount ceramic
capacitor of 0.1 mF placed as close as possible to the device. More
effective decoupling is provided by placing a 100 pF capacitor in
parallel and including a 4.7 W resistor in series with the supply.
Attention should be paid to voltage drops. A ferrite bead is a
better choice than the resistor where a smaller drop is required.
Input-Output Interface
A broadband 50 W input termination can be achieved by
using a 1:2 turns-ratio transformer, as shown in Figure 3.
This also can be used to convert a single-ended input signal
to a balanced differential form at the inputs of the AD8369.
As in all high frequency applications, the trace impedance
should be maintained right up to the input pins by careful
design of the PC board traces, as described in the PCB
Layout Considerations section.
Reducing Gain Sensitivity to Input and Output Impedance
Variation
The lot-to-lot variations in gain mentioned previously can, in
principle, be eliminated by adjustments to the source and load.
Define a term  as a function of the input and output resistances
of the AD8369 and the source and load resistances presented to it:
RR
RR
SOURCE INPUT
OUTPUT LOAD
=
()
=
()
a
a
For a 50 W source,  = 0.25. Then the load resistance for zero
sensitivity to variations must be 800 W. Put more simply:
RRRR
SOURCE LOAD INPUT OUTPUT
()()
=
()( )
= 200
2
In general, there is a loss factor, 1/(1+ ), at each interface so
the
overall gain reduction due to source and output loading is
40 log
10
(1 + ). In this case, the input and output loss factors
are 0.8 (1.94 dB) at each interface so the overall gain is
reduced by 3.88 dB.
Operation from a Single-Sided Source
While there are distinct benefits of driving the AD8369 with a
well-balanced input, in terms of distortion and gain conform-
ance at high frequencies, satisfactory operation will often be
possible when a single-sided source is ac-coupled directly to pin
INHI, and pin INLO is ac-grounded via a second capacitor. This
mode of operation takes advantage of the good HF common-mode
rejection of the input system. The capacitor values are, as always,
selected to ensure adequate transmission at low frequencies.
0.1␮F
R
L
0.1␮F
CONTROL INTERFACE
SOURCE
910111213141516
PWUP VPOS SENB FILT CMDC OPHI
INHI
COMM
INLO DENBCOMM BIT0 BIT1 BIT2 BIT3
AD8369
OPLO
0.1␮F
0.1␮F
V
S
87654321
0.1␮F
50⍀
0.1␮F
0.1␮F
Figure 4. Single-Ended-to-Differential Application Example