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PARALLEL AND SERIAL INTERFACE TIMING
SCLK
CS
SENB
B-LSB B-MSB A-LSBX
X
ALWAYS HIGH
SDAT
t
5
t
6
t
1
t
2
t
3
t
4
A-MSB
07584-003
Figure 2. SPI Port Timing Diagram
t
9
t
7
t
8
t
10
GAIN A, GAIN B
ALWAYS LOW
DENA
DENB
BIT[5:0]
SENB
GAIN A GAIN B
07584-004
Figure 3. Parallel Port Timing Diagram
