Datasheet

AD8366
Rev. A | Page 4 of 28
Parameter Test Conditions/Comments Min Typ Max Unit
10 MHz
Noise Figure Maximum gain 11.4 dB
Minimum gain 18 dB
Second Harmonic 2 V p-p output, maximum gain −97 dBc
2 V p-p output, minimum gain −96 dBc
Third Harmonic 2 V p-p output, maximum gain −97 dBc
2 V p-p output, minimum gain −90 dBc
OIP3
1
2 V p-p composite, maximum gain 38 dBVrms
2 V p-p composite, minimum gain 36 dBVrms
OIP2
1
2 V p-p composite, maximum gain 72 dBVrms
2 V p-p composite, minimum gain 76 dBVrms
Output 1 dB Compression Point
1
Maximum gain 7 dBVrms
Minimum gain 6.7 dBVrms
50 MHz
Noise Figure Maximum gain 11.8 dB
Minimum gain 18.2 dB
Second Harmonic 2 V p-p output, maximum gain −82 dBc
2 V p-p output, minimum gain −84 dBc
Third Harmonic 2 V p-p output, maximum gain −80 dBc
2 V p-p output, minimum gain −71 dBc
OIP3
1
2 V p-p composite, maximum gain 32 dBVrms
2 V p-p composite, minimum gain 26 dBVrms
OIP2
1
2 V p-p composite, maximum gain 71 dBVrms
2 V p-p composite, minimum gain 78 dBVrms
Output 1 dB Compression Point
1
Maximum gain 6.7 dBVrms
Minimum gain 6.7 dBVrms
DIGITAL LOGIC SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5
Input High Voltage, V
INH
2.2 V
Input Low Voltage, V
INL
1.2 V
Input Capacitance, C
IN
1 pF
Input Resistance, R
IN
50 kΩ
SPI INTERFACE TIMING SENB = high
f
SCLK
Serial clock frequency (maximum) 44.4 MHz
t
1
CS rising edge to first SCLK rising edge (minimum) 7.5 ns
t
2
SCLK high pulse width (minimum) 7.5 ns
t
3
SCLK low pulse width (minimum) 15 ns
t
4
SCLK falling edge to CS low (minimum) 7.5 ns
t
5
SDAT setup time (minimum) 7.5 ns
t
6
SDAT hold time (minimum) 15 ns
PARALLEL PORT TIMING SENB = low
t
7
DENA/DENB high pulse width (minimum) 7.5 ns
t
8
DENA/DENB low pulse width (minimum) 15 ns
t
9
BITx setup time (minimum) 7.5 ns
t
10
BITx hold time (minimum) 7.5 ns
POWER AND ENABLE VPSIA, VPSIB, VPSOA, VPSOB, ICOM, OCOM, ENBL
Supply Voltage Range 4.75 5.25 V
Total Supply Current ENBL = 5 V 180 mA
Disable Current ENBL = 0 V 3.2 mA
Disable Threshold 1.65 V
Enable Response Time Delay following high-to-low transition until device
meets full specifications
150 ns
Disable Response Time Delay following low-to-high transition until device
produces full attenuation
3 μs
1
To convert to dBm for a 200 Ω load impedance, add 7 dB to the dBVrms value.