Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsLinear IC - Op-amp Variable gain LFCSP 32 VQ (5x5)

DC to 600 MHz,

Dual-Digital Variable Gain Amplifiers

AD8366

Rev. A

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FEATURES

Matched pair of differential, digitally controlled VGAs

Gain range: 4.5 dB to 20.25 dB

0.25 dB gain step size

Operating frequency

DC to 150 MHz (2 V p-p)

3 dB bandwidth: 600 MHz

Noise figure (NF)

11.4 dB at 10 MHz at maximum gain

18 dB at 10 MHz at minimum gain

OIP3: 45 dBm at 10 MHz

HD2/HD3

Better than −90 dBc for 2 V p-p output at 10 MHz at

maximum gain

Differential input and output

Adjustable output common-mode

Optional dc output offset correction

Serial/parallel mode gain control

Power-down feature

Single 5 V supply operation

APPLICATIONS

Baseband I/Q receivers

Diversity receivers

Wideband ADC drivers

FUNCTIONAL BLOCK DIAGRAM

VPSIA

IPPA

IPMA

ENBL

ICOM

IPMB

IPPB

VPSIB

BIT0/CS

BIT1/SDAT

BIT2/SCL

BIT3

OCOM

BIT4

BIT 5

DENA

DECA

OFSA

CCMA

VCMA

VPSOA

OPPA

OPMA

SENB

DECB

OFSB

CCMB

VCMB

VPSOB

OPPB

OPMB

DENB

DIGITAL GAIN

CONTROL LOGIC

07584-001

Figure 1.

GENERAL DESCRIPTION

The AD8366 is a matched pair of fully differential, low noise and

low distortion, digitally programmable variable gain amplifiers

(VGAs). The gain of each amplifier can be programmed separately

or simultaneously over a range of 4.5 dB to 20.25 dB in steps of

0.25 dB. The amplifier offers flat frequency performance from dc

to 70 MHz, independent of gain code.

The AD8366 offers excellent spurious-free dynamic range, suitable

for driving high resolution analog-to-digital converters (ADCs).

The NF at maximum gain is 11.4 dB at 10 MHz and increases

~2 dB for every 4 dB decrease in gain. Over the entire gain range,

the HD3/HD2 are better than −90 dBc for 2 V p-p at the output at

10 MHz into 200 Ω. The two-tone intermodulation distortion of

−90 dBc into 200 Ω translates to an OIP3 of 45 dBm (38 dBVrms).

The differential input impedance of 200  provides a well-defined

termination. The differential output has a low impedance of ~25 .

The output common-mode voltage defaults to V

POS

/2 but can

be programmed via the VCMA and VCMB pins over a range

of voltages. The input common-mode voltage also defaults

to V

POS

/2 but can be driven down to 1.5 V. A built-in, dc offset

compensation loop can be used to eliminate dc offsets from prior

stages in the signal chain. This loop can also be disabled if dc-

coupled operation is desired.

The digital interface allows for parallel or serial mode gain

programming. The AD8366 operates from a 4.75 V to 5.25 V

supply and consumes typically 180 mA. When disabled, the

part consumes roughly 3 mA. The AD8366 is fabricated using

Analog Devices, Inc., advanced silicon-germanium bipolar

process, and it is available in a 32-lead exposed paddle LFCSP

package. Performance is specified over the −40°C to +85°C

temperature range.

Summary of content (28 pages)

PAGE 1
DC to 600 MHz, Dual-Digital Variable Gain Amplifiers AD8366 SENB OPMA OPPA VPSOA VCMA CCMA OFSA FUNCTIONAL BLOCK DIAGRAM BIT0/CS VPSIA IPPA BIT1/SDAT IPMA BIT2/SCLK ENBL BIT3 DIGITAL GAIN CONTROL LOGIC ICOM OCOM IPMB BIT4 IPPB BIT 5 VPSIB 07584-001 DENB OPMB OPPB VPSOB VCMB CCMB OFSB DENA DECB Matched pair of differential, digitally controlled VGAs Gain range: 4.5 dB to 20.25 dB 0.
PAGE 2
AD8366 TABLE OF CONTENTS Features .............................................................................................. 1 Output Differential Offset Correction .................................... 15 Applications....................................................................................... 1 Output Common-Mode Control ............................................. 15 Functional Block Diagram .............................................................. 1 Gain Control Interface........
PAGE 3
AD8366 SPECIFICATIONS VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Bandwidth Slew Rate INPUT STAGE Linear Input Swing Differential Input Impedance Minimum Input Common-Mode Voltage Maximum Input Common-Mode Voltage Test Conditions/Comments 3 dB; all gain codes 1 dB; all gain codes Maximum gain Minimum gain IPPA, IPMA, IPPB, IPMB At minimum gain AV = 4.
PAGE 4
AD8366 Parameter 10 MHz Noise Figure Second Harmonic Third Harmonic OIP31 OIP21 Output 1 dB Compression Point1 50 MHz Noise Figure Second Harmonic Third Harmonic OIP31 OIP21 Output 1 dB Compression Point1 DIGITAL LOGIC Input High Voltage, VINH Input Low Voltage, VINL Input Capacitance, CIN Input Resistance, RIN SPI INTERFACE TIMING fSCLK t1 t2 t3 t4 t5 t6 PARALLEL PORT TIMING t7 t8 t9 t10 POWER AND ENABLE Supply Voltage Range Total Supply Current Disable Current Disable Threshold Enable Response Time Disabl
PAGE 5
AD8366 PARALLEL AND SERIAL INTERFACE TIMING CS t3 t2 t1 t4 SCLK SDAT t6 B-LSB B-MSB A-LSB A-MSB ALWAYS HIGH SENB X 07584-003 t5 X Figure 2. SPI Port Timing Diagram DENA DENB SENB GAIN A GAIN B GAIN A, GAIN B t10 t9 t7 t8 ALWAYS LOW Figure 3. Parallel Port Timing Diagram Rev.
PAGE 6
AD8366 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltages, VPSIx and VPSOx ENBL, SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5 IPPA, IPMA, IPPB, IPMB OPPA, OPMA, OPPB, OPMB OFSA, OFSB DECA, DECB, VCMA, VCMB, CCMA, CCMB Internal Power Dissipation θJA (With Pad Soldered to Board) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 1.4 W 45.
PAGE 7
AD8366 32 31 30 29 28 27 26 25 DECA OFSA CCMA VCMA VPSOA OPPA OPMA SENB PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD8366 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 BIT0/CS BIT1/SDAT BIT2/SCLK BIT3 OCOM BIT4 BIT5 DENA NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. 07584-028 DECB OFSB CCMB VCMB VPSOB OPPB OPMB DENB 9 10 11 12 13 14 15 16 VPSIA IPPA IPMA ENBL ICOM IPMB IPPB VPSIB Figure 4. Pin Configuration Table 3. Pin Function Descriptions Pin No.
PAGE 8
AD8366 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted. 22 0.5 20 0.4 14 12 10 0 –0.1 –0.2 –0.3 6 –0.4 5 10 15 20 25 30 35 40 45 50 55 60 –0.5 07584-005 0 GAIN CODE 0 5 10 15 20 25 30 35 40 45 50 55 60 GAIN CODE Figure 8. Gain Error vs. Gain Code, Error Normalized to 10 MHz Figure 5. Gain vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz 21.0 25 20.8 GAIN CODE 63 20 20.6 GAIN CODE 48 15 20.
PAGE 9
AD8366 GAIN CODE 0 GAIN CODE 63 20 18 16 16 16 14 14 14 14 12 12 12 12 10 10 10 10 8 8 8 8 6 6 6 6 4 4 4 4 2 2 2 0 0 0 5 10 15 20 25 30 35 40 45 50 55 60 OP1dB (dBm) 07584-030 0 OP1dB (dBVrms) 18 2 GAIN CODE FREQUENCY (MHz) 50 45 55 45 40 50 40 35 45 35 30 40 25 35 20 30 15 25 15 20 10 0 0 5 10 15 FREQUENCY = 10MHz FREQUENCY = 50MHz 20 25 30 35 40 45 50 55 60 OIP3 (dBm) 25 20 5 10 0 GAIN CODE Figure 12. OIP3 vs.
PAGE 10
AD8366 100 90 90 90 80 80 80 70 70 70 60 60 50 50 40 40 30 30 30 20 20 10 10 10 15 20 25 30 35 40 45 50 55 60 OIP2 (dBm) 0 10 GAIN CODE 0 –30 –40 –40 IMD2 (dBc) –20 –50 –60 –70 –80 –90 –90 20 25 30 35 40 45 50 55 60 GAIN CODE –100 80 90 100 110 120 130 140 150 0 GAIN CODE 0 –10 GAIN CODE 32 GAIN CODE 63 –20 CHANNEL A CHANNEL B GAIN CODE 0 GAIN CODE 63 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 FREQUENCY (MHz) Figure 18.
PAGE 11
AD8366 0 60 –10 50 TA = +85°C TA = +25°C TA = –40°C GAIN CODE 0 GAIN CODE 63 –20 –30 –40 IMD3 (dBc) OIP3 (dBm) 40 30 –50 –60 –70 20 –80 –90 –2 –100 GAIN CODE 0 GAIN CODE 63 –1 0 1 2 3 4 5 POUT PER TONE (dBm) Figure 23. OIP3 vs.
PAGE 12
AD8366 60 300 TA = +85°C TA = +25°C TA = –40°C 55 NOISE SPECTRAL DENSITY (nV/√Hz) 280 240 220 200 180 160 140 30 25 20 15 20 25 30 35 40 45 50 55 60 GAIN CODE 10 0.1 1 30 CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL 28 24 FREQUENCY = 0.5MHz FREQUENCY = 0.
PAGE 13
AD8366 0 140 PSRR GAIN CODE 0 PSRR GAIN CODE 63 –10 130 120 110 –20 100 90 SFDR (dB) PSRR (dB) –30 –40 –50 80 70 60 50 –60 40 –70 30 20 30 40 50 60 70 80 90 100 110 120 130 140 150 FREQUENCY (MHz) 0 07584-036 –90 10 2.0 80 15 20 25 30 35 40 45 50 55 60 GAIN CODE 63 70 1.4 60 1.2 CMRR (dB) 1.0 0.8 GAIN CODE 32 50 40 30 0.6 GAIN CODE 0 20 0.
PAGE 14
AD8366 1.2 1.4 1.0 0.8 0.8 OUTPUT VOLTAGE (V) 10pF 0.4 0.2 0 –0.2 –0.4 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –0.8 –1.0 –1.0 –4 –3 –2 –1 0 1 2 3 4 5 TIME (ns) Figure 41. Large Signal Pulse Response, Gain Code 0, Input Signal 1.2 V p-p, 0 pF and 10 pF Capacitive Loading Conditions 10pF 0.6 –0.6 –1.2 –5 07584-067 OUTPUT VOLTAGE (V) 0.6 –1.2 –5 0pF 1.2 0pF –4 –3 –2 –1 0 1 2 3 4 5 TIME (ns) 07584-068 1.0 Figure 44.
PAGE 15
AD8366 CIRCUIT DESCRIPTION The main signal path is shown in Figure 46. It consists of an input transconductance, a variable-gain cell, and an output transimpedance amplifier. 100Ω AI INM 100Ω 12.5Ω To prevent significant levels of offset from appearing at the outputs of the AD8366, each digitally controlled VGA has a differential offset correction loop, as shown in Figure 47.
PAGE 16
The voltage gain of the AD8366 is well approximated by 25.0 1.0 22.5 0.8 20.0 0.6 17.5 0.4 15.0 0.2 12.5 0 10.0 –0.2 7.5 –0.4 5.0 –0.6 2.5 –0.8 Gain (dB) = GainCode × 0.253 + 4.5 0 Note that at several major transitions (15 to 16, 31 to 32, and 47 to 48), the gain changes significantly less (0 dB step) or significantly more (0.5 dB step) than the desired 0.25 dB step.
PAGE 17
AD8366 APPLICATIONS INFORMATION The output buffers of the AD8366 are low impedance around 25 Ω designed to drive ADC inputs. The output common-mode voltage defaults to VPOS/2; however, it can be adjusted by applying a desired external voltage to VCMA/VCMB. The common-mode voltage can be adjusted from 1.6 V to 3.0 V without significant harmonic distortion degradation. BASIC CONNECTIONS Figure 50 shows the basic connections for operating the AD8366. A voltage from 4.75 V to 5.
PAGE 18
AD8366 LC LOWPASS FILTER ADL5523 RF LO 0 90 TO ADC ADF4350 ADL5523 LC LOWPASS FILTER ADL5380 LC LOWPASS FILTER AD8366 07584-047 PAD FILTER BALUN MATCHING NETWORK LC LOWPASS FILTER Figure 51. Direct Conversion Receiver Block Diagram DIRECT CONVERSION RECEIVER DESIGN A direct conversion receiver directly demodulates an RF modulated carrier to baseband frequencies, where the signals can be detected and the conveyed information recovered.
PAGE 19
AD8366 LOW FREQUENCY IMD3 PERFORMANCE –20 To measure the IMD3 data at low frequencies, wideband transformer baluns from North Hills Signal Processing Corp. were used, specifically the 0301BB and the 0520BB. Figure 55 shows the IMD3 performance vs. frequency for a 2 V p-p composite output. The IMD3 performance was also measured for the combined ADL5380 and AD8366 system, as shown in Figure 56, with an FFT spectrum analyzer.
PAGE 20
AD8366 RFIN BALUN 100pF 100pF VPOS VPOS 24 23 22 21 20 19 GND RFIP RFIN GND ADJ 100pF VCC 0.1µF 1 GND GND 18 2 GND GND 17 3 IHI VCC 13 NC 6 VCC 100pF GND GND 14 LOIN 5 GND LOIP QLO 15 GND 0.1µF 4 ILO ENBL VPOS QHI 16 ADL5380 7 8 9 10 11 12 100pF VPOS 100pF 0.1µF 100pF BALUN LO VPOS VPOS VPOS 0.1µF 0.1µF 0.1µF DECA VPSIA IPPA CCMA 0.01µF VPOS VPSOA 0.01µF 200Ω Q CHANNEL PARALLEL/SERIAL CONTROL INTERFACE Figure 56.
PAGE 21
AD8366 In most direct-conversion receiver designs, it is desirable to select a wanted carrier within a specified band. The desired channel can be demodulated by tuning the LO to the appropriate carrier frequency. If the desired RF band contains multiple carriers of interest, the adjacent carriers would also be down converted to a lower IF frequency. These adjacent carriers can be a problem if they are large relative to the desired carrier because they can overdrive the baseband signal detection circuitry.
PAGE 22
AD8366 CHARACTERIZATION SETUPS Figure 58 and Figure 59 are characterization setups used extensively to characterize the AD8366. Characterization was done on single-ended and differential evaluation boards. The bulk of the characterization was done using an automated VEE program to control the equipment as shown in Figure 58. This setup was used to measure P1dB, OIP3, OIP2, IMD2, IMD3, harmonic distortion, gain, gain error, supply current, and noise density. All measurements were done with a 200 Ω load.
PAGE 23
IEEE IEEE IEEE AD8366 AGILENT E8251D SIGNAL GENERATOR AGILENT E8251A SIGNAL GENERATOR AGILENT E4440A SPECTRUM ANALYZER COMBINER RF SWITCH MATRIX KEITHLEY IEEE RF SWITCH MATRIX KEITHLEY IEEE BAND PASS CH2 RF IN BAND REJECT CH1 RF IN CH2 RF OUT CH1 RF OUT AD8366 EVALUATION BOARD Figure 58. Characterization Setup, Single-Ended Measurements Rev.
PAGE 24
AD8366 Rohde & Schwarz ZVA8 RF SWITCH MATRIX KEITHLEY CH2 IP CH2 IM AD8366 EVALUATION BOARD CH2 IM CH1 OM CH2 OP CH2 OM AGILENT E3631A POWER SUPPLY 07584-070 CH1 OP CH2 IP Figure 59. Characterization Setup, Differential Measurements Rev.
PAGE 25
AD8366 EVALUATION BOARD VPSI_A VPSI_A S5 R57 R53 C29 R73 R80 C31 R72 R68 DENA OPPA IPPB IPMB ICOM ENBL IPMA IPPA S12 C12 C3 C20 T1 R48 R63 R44 R62 R46 R14 R13 C5 T2 R17 R21 R58 R47 R15 R16 R12 C18 C23 R20 R19 C21 U1 R50 S3 VPSI_A VPSI_B VPOS BIT2 C1 Figure 60. Evaluation Board Schematic Rev.
PAGE 26
07584-058 07584-059 AD8366 Figure 61. AD8366 Evaluation Board Printed Circuit Board (PCB), Top Side Figure 62. AD8366 Evaluation Board PCB, Bottom Side Table 5. Evaluation Board Configuration Options Components C1, C13 to C16, R3 to R6 T1, T2, C5, C18, C20, C21, R12 to R21, R44 to R48, R50, R54, R58, R62, R63 T3, T4, C24 to C27, R29 to R31, R33 to R39, R65, R67 to R74, R80 Function Power supply decoupling. Nominal supply decoupling consists of a 0.1 μF capacitor to ground followed by 0.
PAGE 27
AD8366 Components S1, S5, S7, R53, R57, R79, C29, C30, C31 S2, S3, S4, S6, S8, S9, S10 R26, R32, R40 to R43, R61, R64, C23, C33, U1 S11, S12, C9, C10 R10, R22, R24, R28, C22, C28 C2, C3, C11, C12 Function Enable interface includes device enable and data enable. Device enable. The AD8366 is enabled by applying a logic high voltage to the ENBL pin. The device is enabled when the S1 switch is set in the down position (high), connecting the ENBL pin to VPSI_A. Data enable.
PAGE 28
AD8366 OUTLINE DIMENSIONS 5.00 BSC SQ TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 12° MAX 32 1 PIN 1 INDICATOR 2.85 2.70 SQ 2.55 EXPOSED PAD (BOTTOM VIEW) 17 16 9 8 0.20 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.25 0.18 25 24 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.