Datasheet

AD8338 Data Sheet
Rev. A | Page 14 of 20
Linear-in-dB Gain Control, GAIN Pin
To facilitate the use of an 80 dB gain range, the AD8338 has a
linear-in-dB gain control. The gain is controlled by the voltage
at Pin GAIN with respect to the local ground COMM. In normal
operating conditions, adjusting the voltage at Pin GAIN from
0.1 V to 1.1 V adjusts the gain from its lowest value of 0 dB to
its highest value of 80 dB. The basic gain equation is
( )
dB8
mV5.12
−=
GAIN
V
dBG
(2)
where V
GAIN
is in volts.
Alternatively, the gain equation can be expressed as a numerical
gain magnitude
mV250
10398.0
GAIN
V
N
G ×=
(3)
where V
GAIN
is in volts.
Inversion of the Gain Slope, MODE Pin
Pin MODE controls the polarity of the gain adjustment. That is,
Pin MODE allows the slope of the gain function to be inverted.
If Pin MODE is tied to VBAT, the gain of the AD8338 increases
exponentially (or linear-in-dB) with an increase in the voltage
at Pin GAIN. If Pin MODE is tied to COMM, the gain of the
AD8338 decreases exponentially (or linear-in-dB) with an
increase in the voltage at Pin GAIN. Figure 44 shows the two
gain control modes when the AD8338 is configured in normal
operating conditions.
Figure 44. Two Gain Control Modes of the AD8338
Offset Correction Circuit, OFSN Pin
The AD8338 includes an internal offset correction circuit
that cancels out any dc offsets that may be present in the
VGA. Connecting a capacitor, C
OFSN
, between Pin OFSN
and Pin VREF enables the offset correction circuit.
The offset correction circuit uses an internal autozero feedback
loop, which introduces small signal high-pass filter characteris-
tics to the signal path. The −3 dB corner frequency is
OFSN
OFSN
C
f
×Ω×
=
4002
1
π
(4)
Even though the AD8338 exhibits a high-pass filter characteris-
tic in its transfer function when the offset correction circuit is
enabled, the latter should not be used as a high-pass filter due
to the narrow voltage range of dc input voltages the circuit can
reject. If signals at frequencies below the band of interest need
to be rejected, for best performance, incorporate a high-pass
filter preceding the AD8338. This can be achieved by ac-
coupling the inputs as shown in Figure 41.
To provide a dc-coupled signal path, the offset correction
circuit can be disabled by connecting Pin OFSN to Pin COMM.
Exercise caution when operating the AD8338 with the offset
correction circuit disabled, because at large gains, dc offsets
will cause large dc errors at the outputs of the VGA.
80
0
10
20
30
40
50
60
70
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
GAIN (dB)
V
GAIN
(V)
LOW MODE HIGH MODE
11279-103