Datasheet

AD8337
Rev. C | Page 22 of 32
The offset voltage effect of the AD8337, as with all VGAs, can
appear as a complex waveform when observed across the range
of V
GAIN
voltage. Generated by multiple sources, each device has
a unique offset voltage (V
OS
) profile while the GAIN input is
swept through its voltage range. The offset voltage profile seen
in Figure 15 is a typical example. If the V
GAIN
input voltage is
modulated, the output is the product of the V
GAIN
and the dc
profile of the offset voltage. This is observed on a scope as a
small ac signal, as shown in Figure 74. In Figure 74, the signal
applied to the V
GAIN
input is a 1 kHz ramp, and the output voltage
signal is slightly less than 4 mV p-p.
Under certain circumstances, the product of V
GAIN
and the
offset profile plus spikes is a coherent spurious signal within the
signal band of interest and indistinguishable from desired
signals. In general, the slower the ramp applied to the GAIN
Pin, the smaller the spikes are. In most applications, these
effects are benign and not an issue.
THERMAL CONSIDERATIONS
The thermal performance of LFCSPs, such as the AD8337,
departs significantly from that of leaded devices such as the
larger TSSOP or QFSP. In larger packages, heat is conducted
away from the die by the path provided by the bond wires and
the device leads. In LFCSPs, the heat transfer mechanisms are
surface-to-air radiation from the top and side surfaces of the
package and conduction through the metal solder pad on the
mounting surface of the device.
OFFSET VOLTAGE (mV)
–4
6
10
0
4
8
–800
–2
V
GAIN
(mV)
–600 –200–400 400 600200 800
0
2
–10
–8
–6
05575-075

V
S
=
2.5
INPUT
OUTPUT
V
S
= ±2.5V
θ
JC
is the traditional thermal metric used for integrated circuits.
Heat transfer away from the die is a three-dimensional dynamic,
and the path is through the bond wires, leads, and the six
surfaces of the package. Because of the small size of LFCSPs, the
θ
JC
is not measured conventionally. Instead, it is calculated using
thermodynamic rules.
The θ
JC
value of the AD8837 listed in Table 2 assumes that the
tab is soldered to the board and that there are three additional
ground layers beneath the device connected by at least four vias.
For a device with an unsoldered pad, the θ
JC
nearly doubles,
becoming 138°C/W.
Figure 74. Offset Voltage vs. V
GAIN
for a 1 kHz Ramp
The profile of the waveform shown in Figure 74 is consistent
over a wide range of signals from dc to about 20 kHz. Above
20 kHz, secondary artifacts can be generated due to the effects
of minor internal circuit tolerances, as shown in Figure 75.
These artifacts are caused by settling and time constants of the
interpolator circuit and appear at the output as the voltage
spikes, as shown in Figure 75.
PSI (Ψ)
Table 2 lists a subset of the classic theta specification, Ψ
JT
(Psi
junction to top). θ
JC
is the metric of heat transfer from the die to
the case, involving the six outside surfaces of the package. Ψ
(XY)
is a subset of the theta value and the thermal gradient from the
junction (die) to each of the six surfaces. Ψ can be different for
each of the surfaces, but since the top of the package is a fraction of
a millimeter from the die, the surface temperature of the package is
very close to the die temperature. The die temperature is calculated
as the product of the power dissipation and Ψ
JT
. Since the top
surface temperature and power dissipation are easily measured, it
follows that the die temperature is easily calculated. For example,
for a dissipation of 180 mW and a Ψ
JT
of 5.3°C/W, the die
temperature is slightly less than 1°C higher than the surface
temperature.
OFFSET VOLTAGE (mV)
–4
6
10
0
4
8
–800
–2
V
GAIN
(mV)
–600 –200–400 400 600200 800
0
2
–10
–8
–6
V
S
=
2.5
INPUT
OUTPUT
05575-074
SPIKE
SPIKE
V
S
= ±2.5V
BOARD LAYOUT
Because the AD8337 is a high frequency device, board layout is
critical. It is very important to have a good ground plane
connection to the VCOM pin. Coupling through the ground
plane, from the output to the input, can cause peaking at higher
frequencies.
Figure 75. V
OS
Profile for a 50 kHz Ramp