Datasheet

AD8331/AD8332/AD8334
Rev. G | Page 6 of 56
Parameter Test Conditions/Comments Min Typ Max Unit
1
ENABLE INTERFACE
(PIN ENB, PIN ENBL, PIN ENBV)
Logic Level to Enable Power 2.25 5 V
Logic Level to Disable Power 0 1.0 V
Input Resistance Pin ENB 25 kΩ
Pin ENBL 40 kΩ
Pin ENBV 70 kΩ
Power-Up Response Time V
INH
= 30 mV p-p 300 μs
V
INH
= 150 mV p-p 4 ms
HILO GAIN RANGE INTERFACE (PIN HILO)
Logic Level to Select HI Gain Range 2.25 5 V
Logic Level to Select LO Gain Range 0 1.0 V
Input Resistance 50 kΩ
OUTPUT CLAMP INTERFACE (PIN RCLMP; HI OR
LO GAIN)
Accuracy
HILO = LO R
CLMP
= 2.74 kΩ, V
OUT
= 1 V p-p (clamped) ±50 mV
HILO = HI R
CLMP
= 2.21 kΩ, V
OUT
= 1 V p-p (clamped) ±75 mV
MODE INTERFACE (PIN MODE)
Logic Level for Positive Gain Slope 0 1.0 V
Logic Level for Negative Gain Slope 2.25 5 V
Input Resistance 200 kΩ
POWER SUPPLY (PIN VPS1, PIN VPS2,
PIN VPSV, PIN VPSL, PIN VPOS)
Supply Voltage 4.5 5.0 5.5 V
Quiescent Current per Channel
AD8331 20 25 mA
AD8332 22 27.5 32 mA
AD8334 24 29.5 34
Power Dissipation per Channel No signal
AD8331 125 mW
AD8332, AD8334 138 mW
Power-Down Current VGA and LNA disabled
AD8331 50 240 400 μA
AD8332 50 300 600 μA
AD8334 50 600 1200 μA
LNA Current
AD8331 (ENBL) Each channel 7.5 11 15 mA
AD8332, AD8334 (ENBL) Each channel 7.5 12 15 mA
VGA Current
AD8331 (ENBV) 7.5 14 20 mA
AD8332, AD8334 (ENBV) 7.5 17 20 mA
PSRR V
GAIN
= 0 V, f = 100 kHz −68 dB
1
All dBm values are referred to 50 Ω.
2
The absolute gain refers to the theoretical gain expression in Equation 1.
3
Best-fit to linear-in-dB curve.
4
The current is limited to ±1 mA typical.