Datasheet
AD8330 Data Sheet
Rev. F | Page 6 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
PIN 1
INDICATOR
1VPSI
2INHI
3INLO
4MODE
11 OPHI
12 VPSO
10 OPLO
9 CMOP
5
VDBS
6
CMGN
7
COMM
8
VMAG
15
OFST
16
ENB
L
14
VPOS
13
CNTR
TOP VIEW
(Not to Scale)
AD8330
03217-003
Figure 2. 16-Lead LFCSP Pin Configuration
1
S
OPVTSFO
1
6
2
RTNCL
BN
E
15
3
OSPVISPV
1
4
4
IHPO
I
H
N
I
13
5
OLPOOLNI
12
6
POMC
ED
O
M
11
7
GAMVSBDV
10
8
MMOCN
G
MC
9
AD8330
TOP VIEW
(Not to Scale)
03217-004
Figure 3. 16-Lead QSOP Pin Configuration
Table 3. 16-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1
VPSI
Positive Supply for Input Stages.
2 INHI Differential Signal Input, Positive
Polarity.
3 INLO Differential Signal Input, Negative
Polarity.
4 MODE Logic Input: Selects Gain Slope.
High = gain up vs. V
DBS
.
5 VDBS Input for Linear-in-dB Gain Control
Voltage, V
DBS
.
6 CMGN Common Baseline for Gain Control
Interfaces.
7 COMM Ground for Input and Gain Control Bias
Circuitry.
8 VMAG Input for Gain/Amplitude Control, V
MAG
.
9 CMOP Ground for Output Stages.
10 OPLO Differential Signal Output, Negative
Polarity.
11
OPHI
Differential Signal Output, Positive
Polarity.
12 VPSO Positive Supply for Output Stages.
13 CNTR Common-Mode Output Voltage Control.
14 VPOS Positive Supply for Inner Stages.
15 OFST Used in Offset Control Modes.
16 ENBL Power Enable, Active High.
EPAD Exposed Pad. It is recommended that
the pad be soldered to the ground
plane.
Table 4. 16-Lead QSOP Pin Function Descriptions
Pin No. Mnemonic Description
1
OFST
Used in Offset Control Modes.
2 ENBL Power Enable, Active High.
3 VPSI Positive Supply for Input Stages.
4 INHI Differential Signal Input, Positive
Polarity.
5 INLO Differential Signal Input, Negative
Polarity.
6 MODE Logic Input: Selects Gain Slope.
High = gain up vs. V
DBS
.
7 VDBS Input for linear-in-dB Gain Control
Voltage, V
DBS
.
8 CMGN Common Baseline for Gain Control
Interfaces.
9 COMM Ground for Input and Gain Control Bias
Circuitry.
10 VMAG Input for Gain/Amplitude Control, V
MAG
.
11 CMOP Ground for Output Stages.
12
OPLO
Differential Signal Output, Negative
Polarity.
13 OPHI Differential Signal Output, Positive
Polarity.
14 VPSO Positive Supply for Output Stages.
15 CNTR Common-Mode Output Voltage Control.
16 VPOS Positive Supply for Inner Stages.