Datasheet

Data Sheet AD8330
Rev. F | Page 3 of 32
SPECIFICATIONS
V
S
= 5 V, T
A
= 25°C, C
L
= 12 pF on OPHI and OPLO, R
L
= ∞, V
DBS
= 0.75 V, V
MODE
= high, V
MAG
= Pin VMAG open circuit (0.5 V),
V
OFST
= 0 V, differential operation, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
INPUT INTERFACE
Pin INHI, Pin INLO
Full-Scale Input V
DBS
= 0 V, differential drive ±1.4 ±2 V
V
DBS
= 1.5 V ±4.5 ±6.3 mV
Input Resistance Pin-to-pin 800 1 k 1.2 k Ω
Input Capacitance Either pin to COMM 4 pF
Voltage Noise Spectral Density
f = 1 MHz, V
DBS
= 1.5 V; inputs ac-shorted
5
nV/√Hz
Common-Mode Voltage Level 3.0 V
Input Offset Pin OFST connected to Pin COMM 1 mV rms
Drift 2 μV/°C
Permissible CM Range
1
0 V
S
V
Common-Mode AC Rejection f = 1 MHz, 0.1 V rms −60 dB
f = 50 MHz −55 dB
OUTPUT INTERFACE Pin OPHI, Pin OPLO
Small Signal –3 dB Bandwidth 0 V < V
DBS
< 1.5 V 150 MHz
Peak Slew Rate
V
DBS
= 0 V
1500
V/μs
Peak-to-Peak Output Swing ±1.8 ±2 ±2.2 V
V
MAG
≥ 2 V (peaks are supply limited) ±4 ±4.5 V
Common-Mode Voltage Pin CNTR O/C 2.4 2.5 2.6 V
Voltage Noise Spectral Density f = 1 MHz, V
DBS
= 0 V 62 nV/√Hz
Differential Output Impedance
Pin-to-pin
120
150
180
Ω
HD2
2
V
OUT
= 1 V p-p, f = 10 MHz, R
L
= 1 kΩ −62 dBc
HD3
2
V
OUT
= 1 V p-p, f = 10 MHz, R
L
= 1 kΩ −53 dBc
OUTPUT OFFSET CONTROL Pin OFST
AC-Coupled Offset C
HPF
on Pin OFST (0 V < V
DBS
< 1.5 V) 10 mV rms
High-Pass Corner Frequency C
HPF
= 3.3 nF, from OFST to CNTR (scales as 1/C
HPF
) 100 kHz
COMMON-MODE CONTROL
Pin CNTR
Usable Voltage Range 0.5 4.5 V
Input Resistance From Pin CNTR to V
S
/2 4 kΩ
DECIBEL GAIN CONTROL VDBS, CMGN, and MODE pins
Normal Voltage Range CMGN connected to COMM 0 to 1.5 V
Elevated Range CMGN O/C (V
CMGN
rises to 0.2 V) 0.2 to 1.7 V
Gain Scaling Mode high or low 27 30 33 mV/dB
Gain Linearity Error 0.3 V ≤ V
DBS
≤ 1.2 V −0.35 ±0.1 +0.35 dB
Absolute Gain Error V
DBS
= 0 V −2 ±0.5 +2 dB
Bias Current Flows out of Pin VDBS 100 nA
Incremental Resistance 100 MΩ
Gain Settling Time to 0.5 dB Error V
DBS
stepped from 0.05 V to 1.45 V or 1.45 V to 0.05 V 250 ns
Mode Up/Down Pin MODE
Mode Up Logic Level Gain increases with V
DBS
, MODE = O/C 1.5 V
Mode Down Logic Level
Gain decreases with V
DBS
0.5
V
LINEAR GAIN INTERFACE Pin VMAG, Pin CMGN
Peak Output Scaling, Gain vs. V
MAG
See the Circuit Description section 3.8 4.0 4.2 V/V
Gain Multiplication Factor vs. V
MAG
Gain is nominal when V
MAG
= 0.5 V ×2
Usable Input Range 0 5 V
Default Voltage V
MAG
O/C 0.48 0.5 0.52 V
Incremental Resistance 4 kΩ
Bandwidth For V
MAG
≥ 0.1 V 150 MHz