Datasheet

AD8330 Data Sheet
Rev. F | Page 26 of 32
COMM
OPHI
INLO
OPLO
INHI
VPSI
VPSO
CMOP
MODE
VDBS CMGN VMAG
OFST CNTRENBL VPOS
BIAS AND
V-REF
CM MODE AND
OFFSET CONTROL
OUTPUT
STAGES
NC
INPUT,
5mV TO 1V rms
0.1µF
10Ω
GAIN INTERFACE
33nF
R1
10kΩ
0.1µF
0.1µF
4.7Ω
Q2
Q1
SEE
TEXT
C1
0.1µF
0.1µF
OUTPUT,
~1V rms
03217-065
V
S
, 2.7V–6V
OUTPUT
CONTROL
VGA CORE
Figure 64. Simple AGC Amplifier (Preliminary)
When the loop is settled, the average current in Q1 is V
DBS
/R1,
which varies from 2 μA at maximum gain (V
DBS
= 0.2 V) to
17 μA at minimum gain (V
DBS
= 1.7 V). This change in the Q1
current causes an increase of ~0.25 dB over the full gain range
in the differential output of nominally 0.75 dBV at midrange
(3.08 V p-p), corresponding to a 200:1 compression ratio. This
is plotted in Figure 65 for a representative 100 kHz input.
INPUT TO AD8330 (dBV)
1.0
002–04–05–
LEVELED OUTPUT (dBV)
0.8
0.7
0.6
0.5
–30
0.9
–10
03217-066
Figure 65. AGC Output vs. Input Amplitude (Simulation)
The upper panel in Figure 66 shows the time-domain output for
fourteen 3 dB steps in input amplitude from 5.4 mV to 1.7 V.
The waveforms in Figure 65 show the AGC voltage (V
DBS
).
This simple detector exhibits a temperature variation in the
differential output amplitude of about 4 mV/°C. It provides a
fast attack time (an increase in the input is quickly leveled to the
nominal output, due to the high peak currents in Q1) and a
slow release time (a decrease in the input is not restored as
quickly). The voltage at the VDBS pin can be used as an RSSI
output, scaled 30 mV/dB. Note that the attack time can be
halved by adding a second transistor, labeled Q2 in Figure 64.
For operation at lower frequencies, the AGC hold capacitor
must be increased.
WIDE RANGE TRUE RMS VOLTMETER
The AD8362 is an rms responding detector providing a
dynamic range of 60 dB from low frequencies to 2.7 GHz.
This can increase to 110 dB using an AD8330 as a precondi-
tioner, provided the noise bandwidth is limited by an interstage
low-pass or band-pass filter.
The VGA also provides an input port that is easier to drive
than the 200 Ω input of the AD8362. Figure 67 shows the
general scheme.
Both the AD8330 and AD8362 provide linear-in-decibel control
interfaces. Thus, when the output of the AD8362 is used to control
the gain of the AD8330, the functional form is unaffected. The
overall scaling is 33 mV/dB. Figure 68 shows the time domain
response using a loop filter capacitor of 10 nF, for inputs rang-
ing from 10 μV to 1 V rms, that is, a 100 dB measurement range.
TIME (µs)
0
GAIN ERROR (dB)
–1
1
–3
3
10 20
30 40 50 60 70 80 90 100 110 120 130 140 150
–2
0
–4
2
0.75
1.25
0.25
1.75
0.50
1.00
0
1.50
V
DBS
OUTPUT
03217-067
Figure 66. Time Domain Waveforms (Simulation)