Datasheet

Data Sheet AD8330
Rev. F | Page 23 of 32
1.2
0 5ns
10n
s
15n
s
25ns
20ns
1.0
0.8
0.6
0.4
0.2
0
–0.2
0.2
–0.4
–0.6
–0.8
–1.0
–1.2
0
–0.2
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
03217-063
Figure 62. Typical Pulse Response for Figure 61
The bandwidth from Pin VMAG to these outputs is somewhat
higher than from the normal input pins. Thus, when this pin is
used to rapidly modulate the primary signal, some further
experimentation with response optimization may be required.
In general, the AD8330 is very tolerant of a wide range of
loading conditions.
Preserving Absolute Gain
Although the AD8330 is not laser trimmed, its absolute gain
calibration, based mainly on ratios, is very good. Full details are
found in the Specifications section and in the typical performance
curves (see the Typical Performance Characteristics section).
Nevertheless, having finite input and output impedances, the
gain is necessarily dependent on the source and load conditions.
The loss that is incurred when either of these is finite causes an
error in the absolute gain. The absolute gain can also be
uncertain due to the approximately ±20% tolerance in the
absolute value of the input and output impedances.
Often, such losses and uncertainties can be tolerated and
accommodated by a correction to the gain control bias. On the
other hand, the error in the loss can be essentially nulled by
using appropriate modifications to either the source impedance
(R
S
) or the load impedance (R
L
), or both (in some cases by
padding them with series or shunt components).
The formulation for this correction technique was previously
described. However, to simplify its use, Table 5 shows spot
values for combinations of R
S
and R
L
resulting in an overall loss
that is not dependent on sample-to-sample variations in on chip
resistances. Furthermore, this fixed and predictable loss can be
corrected by an adjustment to V
MAG
, as indicated in Table 5.
Table 5. Preserving Absolute Gain
Uncorrected Loss
V
MAG
Required to
Correct Loss
R
S
(Ω) R
L
(Ω) Factor dB
10
15 k
0.980
0.17
0.510
15 10 k 0.971 0.26 0.515
20 7.5 k 0.961 0.34 0.520
30 5.0 k 0.943 0.51 0.530
50 3.0 k 0.907 0.85 0.551
75 2.0 k 0.865 1.26 0.578
100 1.5 k 0.826 1.66 0.605
150 1.0 k 0.756 2.43 0.661
200
750
0.694
3.17
0.720
300 500 0.592 4.56 0.845
500 300 0.444 7.04 1.125
750 200 0.327 9.72 1.531
1 k 150 0.250 12.0 2.000
1.5 k
100
0.160
15.9
3.125
2 k 75 0.111 19.1 4.500
Calculation of Noise Figure
The AD8330 noise is a consequence of its intrinsic voltage noise
spectral density (E
NSD
) and the current noise spectral density
(I
NSD
). Their combined effect generates a net input noise, V
NOISE_IN
,
that is a function of the input resistance of the device (R
I
),
nominally 1 kΩ, and the differential source resistance (R
S
) as
follows:
( )
{ }
2
22
_
++=
S
I
NSDNSDINNOISE
RRIEV
(16)
Note that purely resistive source and input impedances as a conces-
sion to simplicity is assumed. A more thorough treatment of
noise mechanisms, for the case where the source is reactive, is
beyond the scope of these brief notes. Also note that V
NOISE_IN
is
the voltage noise spectral density appearing across INHI and
INLO, the differential input pins. In preparing for the calculation
of the noise figure, V
SIG
is defined as the open-circuit signal
voltage across the source, and V
IN
is defined as the differential
input to the AD8330. The relationship is simply
( )
S
I
I
SIG
IN
RR
RV
V
+
=
(17)
At maximum gain, E
NSD
is 4.1 nV/√Hz, and I
NSD
is 3 pA/√Hz.
Thus, the short-circuit voltage noise is
( ) ( )
( )
{ }
=+Ω+=
2
22
_
0k1Hz/pA3Hz/Vn1.4
INNOISE
V
5.08 nV/√Hz (18)
Next, examine the net noise when R
S
= R
I
= 1 kΩ, often incor-
rectly called the matching condition, rather than source impedance
termination, which is the actual situation in this case.
Repeating the procedure,
( )
( )
( )
2
22
_
kΩ1kΩ1Hz/pA3Hz/nV1.4 ++=
INNOISE
V
= 7.3 nV/√Hz (19)