Datasheet

AD8325
LOGIC INPUTS (TTL/CMOS-Compatible Logic)
(DATEN, CLK, SDATA, TXEN, SLEEP, V
CC
= 5 V: Full Temperature Range)
Parameter
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (V
INH
= 5 V) CLK, SDATA, DATEN
Logic “0” Current (V
INL
= 0 V) CLK, SDATA, DATEN
Logic “1” Current (V
INH
= 5 V) TXEN
Logic “0” Current (V
INL
= 0 V) TXEN
Logic “1” Current (V
INH
= 5 V) SLEEP
Logic “0” Current (V
INL
= 0 V) SLEEP
Min Typ Max Unit
2.1 5.0 V
0 0.8 V
0 20 nA
–600 –100 nA
50 190 mA
–250 –30 mA
50 190 mA
–250 –30 mA
TIMING REQUIREMENTS
(Full Temperature Range, V
CC
= 5 V, T
R
= T
F
= 4 ns, f
CLK
= 8 MHz unless otherwise noted.)
Parameter Min Typ Max Unit
Clock Pulsewidth (T
WH
) 16.0 ns
Clock Period (T
C
) 32.0 ns
Setup Time SDATA vs. Clock (T
DS
) 5.0 ns
Setup Time DATEN vs. Clock (T
ES
) 15.0 ns
Hold Time SDATA vs. Clock (T
DH
) 5.0 ns
Hold Time DATEN vs. Clock (T
EH
) 3.0 ns
Input Rise and Fall Times, SDATA, DATEN, Clock (T
R
, T
F
) 10 ns
T
DS
SDATA
CLK
DATEN
TXEN
ANALOG
OUTPUT
T
ES
VALID DATA WORD G1
MSB. . . .LSB
GAIN TRANSFER (G1)
T
EH
8 CLOCK
CYCLES
GAIN TRANSFER (G2)
T
OFF
T
GS
SIGNAL AMPLITUDE (p-p)
T
ON
T
C
T
WH
VALID DATA WORD G2
Figure 2. Serial Interface Timing
SDATA
CLK
VALID DATA BIT
MSB
MSB-1
MSB-2
T
DS
T
DH
Figure 3. SDATA Timing
REV. A
–3–