Datasheet

Data Sheet AD8324
Rev. B | Page 5 of 16
TIMING REQUIREMENTS
V
CC
= 3.3 V, t
R
= t
F
= 4 ns, f
CLK
= 8 MHz, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
Clock Pulse Width (t
WH
) 16.0 ns
Clock Period (t
C
) 32.0 ns
Setup Time SDATA vs. Clock (t
DS
) 5.0 ns
Setup Time
DATEN
vs. Clock (t
ES
)
15.0 ns
Hold Time SDATA vs. Clock (t
DH
) 5.0 ns
Hold Time
DATEN
vs. Clock (t
EH
)
3.0
ns
Input Rise and Fall Times, SDATA,
DATEN
, Clock (t
R
, t
F
)
10 ns
Timing Diagrams
Figure 3. Serial Interface Timing
Figure 4. SDATA Timing
t
DS
CLK
VALID DATA-WORD G1
MSB . . . LSB
SDATA
DATEN
TXEN
ANALOG
OUTPUT
VALID DATA-WORD G2
8 CLOCK CYCLES
GAIN TRANSFER (G1) GAIN TRANSFER (G2)
SIGNAL AMPLITUDE (p-p)
t
C
t
WH
t
ES
t
EH
t
OFF
t
GS
t
CN
04339-0-003
CLK
SDATA
MSB
MSB-1 MSB-2
VALID DATA BIT
t
DS
t
DH
04339-0-004