Datasheet

AD8310
Rev. F | Page 5 of 24
01084-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INLO 1 INHI 8
COMM 2 ENBL 7
OFLT
3
BFIN
6
VPOS 5
AD8310
TOP VIEW
(Not to Scale)
VOUT 4
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2.
2 COMM Common Pin. Usually grounded.
3 OFLT Offset Filter Access. Nominally at about 1.75 V.
4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load.
5 VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current.
6 BFIN Buffer Input. Used to lower postdetection bandwidth.
7 ENBL CMOS Compatible Chip Enable. Active when high.
8 INHI Second of Two Balanced Inputs. Biased roughly to VPOS/2.