Datasheet

AD8305
Rev. B | Page 11 of 24
GENERAL STRUCTURE
The AD8305 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and is also
useful in many nonoptical applications. These notes explain the
structure of this unique style of translinear log amp. Figure 33 is
a simplified schematic showing the key elements.
BIAS
GENERATOR
VLOG
COMM
VNEG (NORMALLY GROUNDED)
VSUM
INPT
0.5V
80kΩ
0.5V
0.5V
V
BE2
V
BE2
V
BE1
V
BE1
44µA/dec
I
REF
I
PD
6.69kΩ
Q2
Q1
PHOTODIODE
INPUT CURRENT
COMM
20kΩ
451Ω
VREF
VRDZ
IREF
14.2kΩ
2.5V
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T × K
03053-033
Figure 33. Simplified Schematic
The photodiode current, I
PD
, is received at Pin INPT. The
voltage at this node is essentially equal to those on the two
adjacent guard pins, VSUM and IREF, due to the low offset
voltage of the JFET op amp. Transistor Q1 converts the input
current I
PD
to a corresponding logarithmic voltage, as shown in
Equation 1. A finite positive value of V
SUM
is needed to bias the
collector of Q1 for the usual case of a single-supply voltage. This
is internally set to 0.5 V, that is, one fifth of the reference voltage
of 2.5 V appearing on Pin VREF. The resistance at the VSUM
pin is nominally 16 kΩ; this voltage is not intended as a general
bias source.
The AD8305 also supports the use of an optional negative
supply voltage, V
N
, at Pin VNEG. When V
N
is −0.5 V or more
negative, VSUM may be connected to ground; thus, INPT and
IREF assume this potential. This allows operation as a voltage-
input logarithmic converter by the inclusion of a series resistor
at either or both inputs. Note that the resistor setting I
REF
needs
to be adjusted to maintain the intercept value. It should also be
noted that the collector-emitter voltages of Q1 and Q2 are now
the full V
N
, and effects due to self-heating causes errors at large
input currents.
The input dependent, V
BE1
, of Q1 is compared with the reference
V
BE2
of a second transistor, Q2, operating at I
REF
. This is generated
externally, to a recommended value of 10 µA. However, other
values over a several-decade range can be used with a slight
degradation in law conformance (see Figure 3).
THEORY
The base-emitter voltage of a BJT (bipolar junction transistor)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:
V
BE
= kT/qIn(I
C
/I
S
) (1)
where:
I
C
is its collector current.
I
S
is a scaling current, typically only 10
−17
A.
kT/q is the thermal voltage, proportional to absolute
temperature (PTAT) and is 25.85 mV at 300 K.
The current, I
S
, is never precisely defined and exhibits an even
stronger temperature dependence, varying by a factor of
roughly a billion between −35°C and +85°C. Thus, to make use
of the BJT as an accurate logarithmic element, both of these
temperature dependencies must be eliminated.
The difference between the base-emitter voltages of a matched
pair of BJTs, one operating at the photodiode current I
PD
and the
second operating at a reference current I
REF
, can be written as:
V
BE1
− V
BE2
= kT/q In(I
C
/I
S
) − kT/q In(I
REF
/I
S
)
= In(10)kT/qlog
10
(I
PD
/I
REF
)
= 59.5 mVlog
10
(I
PD
/I
REF
)(T = 300 K) (2)
The uncertain and temperature dependent saturation current
IS, which appears in Equation 1, has thus been eliminated. To
eliminate the temperature variation of kT/q, this difference
voltage is processed by what is essentially an analog divider.
Effectively, it puts a variable under Equation 2. The output of
this process, which also involves a conversion from voltage-
mode to current-mode, is an intermediate, temperature-
corrected current:
I
LOG
= I
Y
log
10
(I
PD
/I
REF
) (3)
where I
Y
is an accurate, temperature-stable scaling current that
determines the slope of the function (the change in current per
decade). For the AD8305, I
Y
is 44 µA, resulting in a temperature
independent slope of 44 mA/decade, for all values of I
PD
and
I
REF
. This current is subsequently converted back to a voltage-
mode output, V
LOG
, scaled 200 mV/decade.
It is apparent that this output should be zero for I
PD
= I
REF
and
would need to swing negative for smaller values of input
current. To avoid this, I
REF
would need to be as small as the
smallest value of I
PD
. However, it is impractical to use such a
small reference current as 1 nA. Accordingly, an offset voltage is
added to V
LOG
to shift it upward by 0.8 V when Pin VRDZ is
directly connected to VREF. This has the effect of moving the
intercept to the left by four decades, from 10 µA to 1 nA:
I
LOG
= I
Y
log
10
(I
PD
/I
INTC
) (4)
where I
INTC
is the operational value of the intercept current. To
disable this offset, Pin VRDZ should be grounded, then the
intercept I
INTC
is simply I
REF
. Because values of I
PD
< I
INTC
result in
a negative VLOG, a negative supply of sufficient value is