Datasheet

REV. A
–2–
AD8300–SPECIFICATIONS
+3 V OPERATION
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution N [Note 1] 12 Bits
Relative Accuracy INL –2 ±1/2 +2 LSB
Differential Nonlinearity
2
DNL Monotonic –1 ±1/2 +1 LSB
Zero-Scale Error V
ZSE
Data = 000
H
+1/2 +3 mV
Full-Scale Voltage
3
V
FS
Data = FFF
H
2.039 2.0475 2.056 Volts
Full-Scale Tempco TCV
FS
[Notes 3, 4] 16 ppm/°C
ANALOG OUTPUT
Output Current (Source) I
OUT
Data = 800
H
, ∆V
OUT
= 5 LSB 5 mA
Output Current (Sink) I
OUT
Data = 800
H
, ∆V
OUT
= 5 LSB 2 mA
Load Regulation L
REG
R
L
= 200 Ω to ∞, Data = 800
H
1.5 5 LSB
Output Resistance to GND R
OUT
Data = 000
H
30 Ω
Capacitive Load C
L
No Oscillation
4
500 pF
LOGIC INPUTS
Logic Input Low Voltage V
IL
0.6 V
Logic Input High Voltage V
IH
2.1 V
Input Leakage Current I
IL
10 µA
Input Capacitance C
IL
10 pF
INTERFACE TIMING
SPECIFICATIONS
4, 5
Clock Width High t
CH
40 ns
Clock Width Low t
CL
40 ns
Load Pulsewidth t
LDW
50 ns
Data Setup t
DS
15 ns
Data Hold t
DH
15 ns
Clear Pulsewidth t
CLRW
40 ns
Load Setup t
LD1
15 ns
Load Hold t
LD2
40 ns
Select t
CSS
40 ns
Deselect t
CSH
40 ns
AC CHARACTERISTICS
4
Voltage Output Settling Time t
S
To ±0.2% of Full Scale 7 µs
To ±1 LSB of Final Value
6
14 µs
Output Slew Rate SR Data = 000
H
to FFF
H
to 000
H
2.0 V/µs
DAC Glitch 15 nV/s
Digital Feedthrough 15 nV/s
SUPPLY CHARACTERISTICS
Power Supply Range V
DD RANGE
DNL < ±1 LSB 2.7 5.5 V
Positive Supply Current I
DD
V
DD
= 3 V, V
IL
= 0 V, Data = 000
H
1.2 1.7 mA
V
DD
= 3.6 V, V
IH
= 2.3 V, Data = FFF
H
1.9 3.0 mA
Power Dissipation P
DISS
V
DD
= 3 V, V
IL
= 0 V, Data = 000
H
3.6 5.1 mW
Power Supply Sensitivity PSS ∆V
DD
= ±5% 0.001 0.005 %/%
NOTES
1
LSB = 0.5 mV for 0 V to +2.0475 V output range.
2
The first two codes (000
H
, 001
H
) are excluded from the linearity error measurement.
3
Includes internal voltage reference error.
4
These parameters are guaranteed by design and not subject to production testing.
5
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
(@ V
DD
= +5 V ⴞ 10%, –40ⴗC ≤ T
A
≤ +85ⴗC, unless otherwise noted)