Datasheet
AD8264
Rev. A | Page 35 of 40
+V
+V
IPN1
OPP1
OPP2
IPN2
IPP2
IPP3
IPN3
OPP3
IPP4
COMM
GNH4
GNH3
VOCM
VPOS
VNEG
OFS4
IPP1
COMM
GNH1
GNH2
GNLO
VPOS
VNEG
OFS1
VOL1
VOH1
VOH2
VOL2
VGA2
VGA3
VOL3
VOH3
OPP4
VOH4
IPN4
VOL4
OFS3
VGA4
OFS2
VGA1
–V
–V
OFS12
OFS34
GNLO
VOCM
GN1_2
PIN 0
EXPOSED PADDLE
IN3
OP1_2
12
C23
0.1µF
15 20191817161413
R17
DNI
R16
DNI
R28
DNI
L3
FB
L4
FB
IN4
11
L1
FB
VPOS
21
30
29
28
27
26
25
24
23
22
VGA2
VGA3
VGA4
VGA1
39 36 31323334353738
40
R11
49.9Ω
R10
DNI
+
+
R9
DNI
OP3_4
10
1
2
3
4
5
6
7
8
9
R19
DNI
R29
DNI
IN2
R73
0Ω
R23
DNI
R31
DNI
OPP12
OPP34
VO_CM
VOUT_3
VOUT_4
VOUT_2
VOUT_1
OFS_12
GN1_2
GND2 GND3 GND4 GND5 GND6GND1
+V
–V
IN_4
IN_3
IN_2
OP34
OP12
GN3_4
GN34
VGA_4
VGA3
VGA2
VGA_1
C19
0.1µF
C20
0.1µF
C34
10µF
C33
10µF
L2
FB
OPP_3
OPP_4
OPP_2
OPP_1
C24
0.1µF
OFS_34
R32
DNI
R49
0Ω
R86
0Ω
R47
0Ω
R48
0Ω
R51
0Ω
IN_1
R1
453Ω
IN1
R7
453Ω
R22
DNI
R45
49.9Ω
R46
49.9Ω
R6
453Ω
R25
DNI
R20
DNI
R78
0Ω
R72
0Ω
R17
49.9Ω
C22
0.1µF
C21
0.1µF
R80
0Ω
R79
0Ω
R70
0Ω
R71
0Ω
R8
453Ω
R64
0Ω
R63
0Ω
R65
0Ω
R66
0Ω
R67
453Ω
R69
453Ω
R57
0Ω
R58
0Ω
R56
0Ω
R55
0Ω
07736-088
PIN 0: EXPOSED PADDLE
R24
DNI
Figure 118. AD8264-EVALZ Schematic
The SMA connectors, VGA1 through VGA4, enable signal
monitoring at these nodes, with 453 Ω resistors for protecting
the device. These resistors can be shorted at the discretion of
the user if wide bandwidth is desired. The differential outputs
are provided with 0.1” spacing 2-pin headers, which fit the low
capacitance Tektronix differential scope probe P6045 model.
Note that the gain control input of the AD8264 is differential.
Each channel has its own gain control pin (GNHx); however,
pairs of pins are connected together on the evaluation board
and connected to a test loop. The 2-pin headers are provided for
jumpers to connect the gain pins to ground, preventing the
quiescent gain control voltage at the GNHx pins from floating
high. The low sides of the gain controls for each channel are
internally connected in the AD8264, and a 2-pin header with
jumper is provided to connect this pin (GNLO) to ground as well.
A similar arrangement of 2-pin headers is provided for the output
offset voltage. As shipped, the offset pins are connected to ground,
preventing the pins from floating high.
For connecting to an ADC, remove the jumpers at the OF1_2
and OF3_4 headers and connect the appropriate offset voltage
at the test loops, OF12 and OF34. If the VOCM pin is buffered,
it can be connected to the reference of the ADC.