Datasheet

AD8251
Rev. B | Page 17 of 24
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
A1 A0 Gain
−V
S
Low Low 1
−V
S
Low High 2
−V
S
High Low 4
−V
S
High High 8
Latched Gain Mode
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8251 can be set using
WR
as a latch,
allowing other devices to share A0 and A1. shows a
schematic using this method, known as latched gain mode. The
AD8251 is in this mode when
Figure 53
WR
is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0 and A1
are read on the downward edge of the
WR
signal as it transitions
from logic high to logic low. This latches in the logic levels on
A0 and A1, resulting in a gain change. See the truth table in
for more information on these gain changes. Table 6
+15
V
–15V
A0
A1
WR
+IN
–IN
10F0.1µF
10F0.1µF
DGND DGND
REF
AD8251
A0
A1
WR
+5V
+5V
+5V
0V
0V
0V
G = PREVIOUS
STATE
G = 8
+
–
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8.
06287-052
Figure 53. Latched Gain Mode, G = 8
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
A1 A0 Gain
High to low Low Low Change to 1
High to low Low High Change to 2
High to low High Low
Change to 4
High to low High High
Change to 8
Low to low X
1
X
1
No change
Low to high X
1
X
1
No change
High to high X
1
X
1
No change
1
X = don’t care.
On power-up, the AD8251 defaults to a gain of 1 when in latched
gain mode. In contrast, if the AD8251 is configured in transparent
gain mode, it starts at the gain indicated by the voltage levels on
A0 and A1 at power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 must be held for
a minimum setup time, t
SU
, before the downward edge of
WR
latches in the gain. Similarly, they must be held for a minimum
hold time of t
HD
after the downward edge of
WR
to ensure that
the gain is latched in correctly. After t
HD
, A0 and A1 can change
logic levels, but the gain does not change (until the next
downward edge of
WR
). The minimum duration that
WR
can
be held high is t
WR-HIGH
, and the minimum duration that
WR
can be held low is t
WR-LOW
. Digital timing specifications are
listed in The time required for a gain change is
dominated by the settling time of the amplifier. A timing
diagram is shown in .
Table 2.
Figure 54
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8251. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog portions
of the board. Pull-up or pull-down resistors should be used to
provide a well-defined voltage at the A0 and A1 pins.
A0, A1
WR
t
SU
t
HD
t
WR-HIGH
t
WR-LOW
0
6287-053
Figure 54. Timing Diagram for Latched Gain Mode