Datasheet

AD8251-EVALZ
Rev. 0 | Page 3 of 4
Latched Gain Mode
Some applications have multiple programmable devices such
as multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8251 can be set using
WR
as a
latch, allowing other devices to share A0 and A1.
Figure 3 shows
a schematic using this method, known as latched gain mode.
(On the AD8251-EVALZ, remove the W1, W2, and W3 jumpers,
and drive A0, A1, and
WR
with external logic to test this gain
setting mode.) The AD8251 is in this mode when
WR
is held at
logic high or logic low, typically 5 V and 0 V, respectively. The
voltages on A0 and A1 are read on the downward edge of the
WR
signal as it transitions from logic high to logic low. This
latches in the logic levels on A0 and A1, resulting in a gain
change. See the truth table listing in
Table 4 for more informa-
tion on these gain changes.
+15
V
–15V
A0
A1
WR
+IN
–IN
10μF0.1µF
10μF0.1µF
DGND DGND
REF
AD8251
A0
A1
WR
+5V
+5V
+5V
0V
0V
0V
G = PREVIOUS
STATE
G = 8
+
–
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8.
06838-003
Figure 3. Latched Gain Mode, G = 8
Table 4. Truth Table Logic Levels for Latched Gain Mode
WR
1
A1
1
A0
1
Gain
High to low Low Low Change to 1
High to low Low High Change to 2
High to low High Low Change to 4
High to low High High Change to 8
Low to low X
2
X
2
No change
Low to high X
2
X
2
No change
High to high X
2
X
2
No change
1
Jumper W1, Jumper W2, and Jumper W3 must be removed and external
logic must be used to test latched gain mode.
2
X = don’t care.
On power-up, the AD8251 defaults to a gain of 1 when in
latched gain mode. In contrast, if the AD8251 is configured in
transparent gain mode, it starts at the gain indicated by the
voltage levels on A0 and A1 upon power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 have to be held
for a minimum setup time, t
SU
, before the downward edge of
WR
latches in the gain. Similarly, they must be held for a
minimum hold time of t
HD
after the downward edge of
WR
to
ensure that the gain is latched in correctly. After t
HD
, A0 and A1
may change logic levels but the gain does not change (until the
next downward edge of
WR
). The minimum duration that
WR
can be held high is t
WR
-HIGH
, and t
WR
-LOW
is the minimum
duration that
WR
can be held low. Digital timing specifications
are listed in the Specification section of the
AD8251 data sheet.
The time required for a gain change is dominated by the settling
time of the amplifier. A timing diagram is shown in
Figure 4.
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8251. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog
portions of the board.
A0, A1
WR
t
SU
t
HD
t
WR-HIGH
t
WR-LOW
0
6838-004
Figure 4. Timing Diagram for Latched Gain Mode