Datasheet

AD8251-EVALZ
Rev. 0 | Page 2 of 4
EVALUATION BOARD HARDWARE
QUICK START GUIDE
By default, the AD8251-EVALZ is configured for gain change
using the on-board switches, SW1 and SW2, as shown in
Table 1.
Table 1. Gain Setting Using the On-Board Switches
W3 (Jumper) SW2 SW1 Gain
In place Low Low 1
In place Low High 2
In place High Low 4
In place High High 8
Table 2. Default Settings (From the Factory)
Name Default Status
W1, W2, W3 In place (tied)
JP1, JP3, R1, R2, R3, R5 Shorted by design (on trace)
USING EXTERNAL LOGIC TO CHANGE GAIN
The AD8251-EVALZ accepts external logic signals such as
those from logic generators or FPGAs. To change gains using
external logic signals, Jumper W1, Jumper W2, and Jumper W3
must be removed. Only then are the A0, A1, and
WR
pins on
the AD8251 directly tied to TP3, TP4, and TP5 (and to the
respective SMA connectors). External logic can be tied via the
test points TP3, TP4, and TP5, or via the respective SMA
connector.
TERMINATION
The AD8251-EVALZ has 50 Ω traces leading to the A0, A1, and
WR
pins. However, it does not have terminations to those pins.
If terminations are added, remove Jumper W1, Jumper W2, and
Jumper W3.
RFI FILTER
An RFI filter pattern is included at the input traces of the
AD8251-EVALZ. R1 and R2 are shorted. The shorted traces
must be cut before R1 and R2 are placed on the board.
OUTPUT FILTER
An output filter pattern is included at the output trace of the
AD8251-EVALZ. To use R3 or R5 in a filter, cut the shorted
traces prior to placing resistors in those locations.
REFERENCE
To level shift the output, a nonzero reference voltage can be applied
to REF. By default, REF is tied to analog GND. Cutting the trace
at JP1 opens the connection between REF and analog GND.
ANALOG AND DIGITAL GROUND
Analog and digital grounds are tied at JP3. To sever the
connection between them, JP3 can be cut with a knife to open
the connection between the two grounds.
GAIN SELECTION (FROM AD8251 DATA SHEET)
This section shows users how to configure the AD8251 for basic
operation. Logic low and logic high voltage limits are listed in
the Specifications section of the
AD8251 data sheet. Typically,
logic low is 0 V and logic high is 5 V; both voltages are meas-
ured with respect to DGND. Refer to the specifications table of
the
AD8251 for the permissible voltage range of DGND. The
gain of the AD8251 can be set using two methods.
Transparent Gain Mode
The easiest way to set the gain is to program it directly via a
logic high or logic low voltage applied to A0 and A1.
Figure 2
shows an example of this gain setting method, referred to
throughout the data sheet as transparent gain mode. Tie
WR
to
the negative supply to engage transparent gain mode. (On the
AD8251-EVALZ board, put Jumper W3 in place.) In this mode,
any change in voltage applied to A0 and A1 from logic low to
logic high, or vice versa, immediately results in a gain change.
Table 3 is the truth table for transparent gain mode and Figure 2
shows the AD8251 configured in transparent gain mode.
+15
V
–15V
–15V
A0
A1
WR
+IN
+5V
+5V
–IN
10μF0.1µF
10μF0.1µF
G = 8
DGND DGND
REF
AD8251
NOTE:
1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −
V
S
.
THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE
THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE
SET TO LOGIC HIGH, RESULTING IN A GAIN OF 8.
0
6838-002
Figure 2. Transparent Gain Mode, A0 and A1 = High, G = 8
Table 3. Truth Table Logic Levels for Transparent Gain Mode
WR
(W3) A1 (SW2) A0 (SW1) Gain
−V
S
(in place) Low Low 1
−V
S
(in place) Low High 2
−V
S
(in place) High Low 4
−V
S
(in place) High High 8