Datasheet

REV. C
AD824
–5–
WAFER TEST LIMITS
Parameter Symbol Conditions Limit Unit
Offset Voltage V
OS
1.0 mV max
Input Bias Current I
B
12 pA max
Input Offset Current I
OS
20 pA
Input Voltage Range V
CM
–0.2 to 3.0 V min
Common-Mode Rejection Ratio CMRR V
CM
= 0 V to 2 V 66 dB min
Power Supply Rejection Ratio PSRR V = + 2.7 V to +12 V 70 mV/V
Large Signal Voltage Gain A
VO
R
L
= 2 kW 15 V/mV min
Output Voltage High V
OH
I
SOURCE
= 20 mA 4.975 V min
Output Voltage Low V
OL
I
SINK
= 20 mA25 mV max
Supply Current/Amplifier I
SY
V
O
= 0 V, R
L
= • 600 mA max
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
(@ V
S
= 5.0 V, V
CM
= 0 V, T
A
= 25C unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –V
S
– 0.2 V to +V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Output Short Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
AD824A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Junction Temperature Range
R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C
Package Type q
JA
2
q
JC
Unit
14-Lead SOIC (R) 120 36 ∞C/W
16-Lead SOIC (R) 92 27 ∞C/W
NOTES
1
Absolute maximum ratings apply to packaged parts unless otherwise noted.
2
q
JA
is specified for the worst case conditions, i.e., q
JA
is specified for device in socket
for P-DIP packages; q
JA
is specified for device soldered in circuit board for SOIC
package.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD824AR-14 –40∞C to +85∞C 14-Pin SOIC R-14
AD824AR-14-3V –40∞C to +85∞C 14-Pin SOIC R-14
AD824AR-16 –40∞C to +85∞C 16-Pin SOIC R-16
R1 R2
+IN
J1 J2
R13
–IN
R15
Q4
Q5
Q6
R9
I5
V
CC
C3
Q7
C2
Q22
Q19
Q21 Q27
Q18 Q29
Q20
Q23
R7
C4
V
OUT
Q24 Q25
Q31
Q28
R17
Q26
C1
I4I3I2I1
R12 R14
Q2
Q8
Q3
V
EE
I6
Figure 1. Simplified Schematic of 1/4 AD824
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD824 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE