Datasheet

Data Sheet AD822
Rev. J | Page 13 of 24
FREQUENCY
(Hz)
100
–20
80
60
40
20
0
10 10M
100
OPEN-LOOP GAIN (dB)
1k 10k 100k 1M
100
–20
80
60
40
20
0
PHASE MARGIN (Degrees)
PHASE
GAIN
C
L
= 100pF
R
L
= 2kΩ
00874-016
Figure 16. Open-Loop Gain and Phase Margin vs. Frequency
FREQUENCY (Hz)
1k
100
100
10M1k
OUTPUT IMPEDANCE (Ω)
10k 100k 1M
10
1
0.1
0.01
A
CL
= +1
V
S
= ±15V
00874-017
Figure 17. Output Impedance vs. Frequency
SETTLING TIME (µs)
16
12
–16
0 51
OUTPUT SWING FROM 0TO ±VOLTS
2 3 4
0
–4
–8
–12
8
4
ERROR
1%
0.1%
1%
0.01%
0.01%
00874-018
Figure 18. Output Swing and Error vs. Settling Time
90
80
0
40
30
20
10
60
50
70
COMMON-MODE REJECTION (dB)
FREQUENCY (Hz)
10M100 1k 10k 100k
1M10
V
S
= ±15V
V
S
= 0
V
, +5V
V
S
= 0V, +3V
00874-019
Figure 19. Common-Mode Rejection vs. Frequency
+125°C
–55°C
+25°C
POSITIVE
RAIL
NEGA
TIVE
RAIL
COMMON-MODE VOLT
AGE FROM SUPPLY RAILS (V)
5
4
0
–1 3
COMMON-MODE ERROR VOLT
AGE (mV)
3
2
1
–55°C
+125°C
210
00874-020
Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage from
Supply Rails (V
S
− V
CM
)
LOAD CURRENT (mA)
1000
100
0
0.001 1000.01
OUTPUT SATURATION VOLTAGE (mV)
0.1 1 10
10
V
S
– V
OH
V
OL
– V
S
00874-021
Figure 21. Output Saturation Voltage vs. Load Current