Datasheet

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HDMI/DVI Buffer with Equalization

Data Sheet

AD8195

Rev. B

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FEATURES

1 input, 1 output HDMI/DVI link

Enables HDMI 1.3a-compliant front panel input

4 TMDS channels per link

Supports 250 Mbps to 2.25 Gbps data rates

Supports 25 MHz to 225 MHz pixel clocks

Equalized inputs for operation with long HDMI cables

(20 m at 2.25 Gbps)

Preemphasized outputs

Fully buffered unidirectional inputs/outputs

50 Ω on-chip terminations

Low added jitter

Transmitter disable feature

Reduces power dissipation

Disables input termination

3 auxiliary buffered channels per link

Bidirectional buffered DDC lines (SDA and SCL)

Bidirectional buffered CEC line with integrated pull-up

resistors (27 kΩ)

Independently powered from 5 V of HDMI input

connector

Logic level translation (3.3 V, 5 V)

Input/output capacitance isolation

Standards compatible: HDMI, DVI, HDCP, DDC, CEC

40-lead LFCSP_VQ package (6 mm × 6 mm)

APPLICATIONS

Front panel buffer for advanced television (HDTV) sets

GENERAL DESCRIPTION

The AD8195 is an HDMI/DVI buffer featuring equalized TMDS

inputs and preemphasized TMDS outputs, ideal for systems with

long cable runs. The AD8195 includes bidirectional buffering

for the DDC bus and bidirectional buffering with integrated

pull-up resistors for the CEC bus. The DDC and CEC buffers

are powered independently of the TMDS buffers so that DDC/

CEC functionality can be maintained when the system is powered

off. The AD8195 meets all the requirements for sink tests as

defined in Section 8 of the HDMI Compliance Test 1.3c.

The AD8195 is specified to operate over the −40°C to +85°C

temperature range.

FUNCTIONAL BLOCK DIAGRAM

IP[3:0]

IN[3:0]

VTTI

OP[3:0]

AMUXVCC

AVEE

VTTO

AVCC

ON[3:0]

VREF_IN VREF_OUT

–

BUFFER

CONTROL

LOGIC

HIGH SPEED BUFFERED

LOW SPEED BUFFERED

PE_EN

TX_EN

COMP

PARALLEL

BIDIRECTIONAL

AD8195

SCL_IN

SDA_IN

SCL_OUT

SDA_OUT

CEC_IN CEC_OUT

07049-001

Figure 1.

TYPICAL APPLICATION

07049-002

MEDIA CENTER

SET-TOP BOX

DVD PLAYER

HDTV SET

4:1 HDMI

SWITCH

AD8195

HDMI

RECEIVER

FRONT PANEL

CONNECTOR

BACK PANEL

CONNECTORS

GAME

CONSOLE

Figure 2. Typical AD8195 Application for HDTV Sets

PRODUCT HIGHLIGHTS

1. Enables a fully HDMI 1.3a-compliant front panel input.

2. Supports data rates of up to 2.25 Gbps, enabling 1080p deep

color (12-bit color) HDMI formats and greater than UXGA

(1600 × 1200) DVI resolutions.

3. Input cable equalizer enables use of long cables; more than

20 meters (24 AWG) at data rates of up to 2.25 Gbps.

4. Auxiliary buffer isolates and buffers the DDC bus and CEC

line for a single chip, fully HDMI 1.3a-compliant solution.

5. Auxiliary buffer is powered independently from the TMDS

link so that DDC/CEC functionality can be maintained

when the system is powered off.

Summary of content (20 pages)

PAGE 1
FUNCTIONAL BLOCK DIAGRAM COMP PARALLEL AVCC AD8195 VTTI IP[3:0] IN[3:0] AMUXVCC AVEE CONTROL LOGIC + 4 – 4 VTTO BUFFER EQ PE HIGH SPEED 4 + 4 – OP[3:0] ON[3:0] BUFFERED VREF_IN VREF_OUT SCL_IN SDA_IN 2 SCL_OUT SDA_OUT 2 CEC_IN CEC_OUT LOW SPEED BUFFERED 07049-001 1 input, 1 output HDMI/DVI link Enables HDMI 1.3a-compliant front panel input 4 TMDS channels per link Supports 250 Mbps to 2.
PAGE 2
AD8195 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................8 General Description .........................................................................
PAGE 3
Data Sheet AD8195 SPECIFICATIONS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AMUXVCC = 5 V, VREF_IN = 5 V, VREF_OUT = 5 V, AVEE = 0 V, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. TMDS PERFORMANCE SPECIFICATIONS Table 1.
PAGE 4
AD8195 Data Sheet AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS Table 2. Parameter DDC CHANNELS Input Capacitance, CAUX Input Low Voltage, VIL Input High Voltage, VIH Output Low Voltage, VOL Output High Voltage, VOH Rise Time Fall Time Leakage CEC CHANNEL Input Capacitance, CAUX Input Low Voltage, VIL Input High Voltage, VIH Output Low Voltage, VOL Output High Voltage, VOH Rise Time Fall Time Pull-Up Resistance Leakage 1 2 Test Conditions/Comments Min DC bias = 2.5 V, ac voltage = 3.
PAGE 5
Data Sheet AD8195 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter AVCC to AVEE VTTI VTTO AMUXVCC VREF_IN VREF_OUT Internal Power Dissipation High Speed Input Voltage High Speed Differential Input Voltage Parallel Control Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature ESD, Human Body Model Input Pins Only All Other Pins Rating 3.7 V AVCC + 0.6 V AVCC + 0.6 V 5.5 V 5.5 V 5.5 V 1.81 W AVCC − 1.4 V < VIN < AVCC + 0.6 V 2.0 V AVEE − 0.
PAGE 6
AD8195 Data Sheet 32 AMUXVCC 31 CEC_OUT 34 SDA_OUT 33 VREF_OUT 35 SCL_OUT 37 AVEE 36 VREF_IN 38 CEC_IN 40 SCL_IN 39 SDA_IN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN0 1 IP0 2 IN1 3 28 TX_EN IP1 4 27 AVEE VTTI 5 AD8195 IN2 6 IP2 7 TOP VIEW (Not to Scale) IN3 8 23 AVCC IP3 9 22 AVCC AVCC 10 21 COMP 30 AVCC 26 AVCC 25 AVCC NOTES 1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF THE PACKAGE THAT AIDS IN HEAT DISSIPATION.
PAGE 7
Data Sheet Pin No. 31 32 33 34 35 36 38 39 40 1 AD8195 Mnemonic CEC_OUT AMUXVCC VREF_OUT SDA_OUT SCL_OUT VREF_IN CEC_IN SDA_IN SCL_IN Type 1 LS I/O Power Reference LS I/O LS I/O Reference LS I/O LS I/O LS I/O Description CEC Output Side. Positive Auxiliary Buffer Supply. 5 V nominal. DDC Output Side Pull-Up Reference Voltage. DDC Output Side Data Line Input/Output. DDC Output Side Clock Line Input/Output. DDC Input Side Pull-Up Reference Voltage. CEC Input Side. DDC Input Side Data Line.
PAGE 8
AD8195 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. HDMI CABLE AD8195 DIGITAL PATTERN GENERATOR SERIAL DATA ANALYZER EVALUATION BOARD REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07049-104 SMA COAX CABLE 0.125UI/DIV AT 2.25Gbps 0.167UI/DIV AT 3.0Gbps Figure 6.
PAGE 9
Data Sheet AD8195 0.125UI/DIV AT 2.25Gbps 0.167UI/DIV AT 3.0Gbps Figure 10 Rx Eye Diagram at TP2 (Cable = 15 Meters, 24 AWG, Data Rate = 3 Gbps) Figure 12. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 15 Meters, 24 AWG, Data Rate = 3 Gbps) Rev. B | Page 9 of 20 07049-212 0.167UI/DIV AT 3.0Gbps 07049-210 250mV/DIV Figure 11. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 20 Meters, 24 AWG, Data Rate = 2.25 Gbps) 250mV/DIV Figure 9 Rx Eye Diagram at TP2 (Cable = 20 Meters, 24 AWG, Data Rate = 2.
PAGE 10
AD8195 Data Sheet TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. HDMI CABLE AD8195 DIGITAL PATTERN GENERATOR SERIAL DATA ANALYZER EVALUATION BOARD TP1 REFERENCE EYE DIAGRAM AT TP1 TP2 TP3 07049-109 SMA COAX CABLE 0.125UI/DIV AT 2.25Gbps 0.167UI/DIV AT 3.0Gbps Figure 15. Tx Eye Diagram at TP2, PE = 0 dB, Data Rate = 3.
PAGE 11
Data Sheet AD8195 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. 0.6 0.6 ALL CABLES = 24 AWG PE = 6dB ALL CABLES = 24 AWG 0.5 0.5 0.4 JITTER (UI) JITTER (UI) 0.4 3.0Gbps 1080p, 12- BIT 0.3 1.65Gbps 0.2 0.3 3.0Gbps 1080p, 12-BIT 0.2 1080p, 8-BIT 1080p, 8-BIT 1.
PAGE 12
AD8195 Data Sheet TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 3 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. 80 50 45 70 40 60 DJ p-p JITTER (ps) JITTER (ps) 35 50 40 DJ p-p 30 30 25 20 15 20 10 10 5 0.5 1.0 1.5 2.0 DIFFERENTIAL INPUT VOLTAGE SWING (V) 0 2.5 07049-120 0 2.9 3.1 3.3 3.5 3.7 INPUT COMMON-MODE VOLTAGE (V) Figure 24. Jitter vs.
PAGE 13
Data Sheet AD8195 THEORY OF OPERATION OUTPUT CHANNELS Each high speed output differential pair is terminated to the 3.3 V VTTO power supply through two single-ended 50 Ω on-chip resistors (see Figure 31). VTTO 50Ω OPx All four high speed TMDS channels are identical; that is, the pixel clock can be run on any of the four TMDS channels. Receive channel compensation is provided for the high speed channels to support long input cables.
PAGE 14
AD8195 Data Sheet PREEMPHASIS AUXILIARY LINES The preemphasized TMDS outputs precompensate the transmitted signal to account for losses in systems with long cable runs. These long cable runs selectively attenuate the high frequency energy of the signal, leading to degraded transition times and eye closure. Similar to a receive equalizer, the goal of the preemphasis filter is to boost the high frequency energy in the signal.
PAGE 15
Data Sheet AD8195 APPLICATIONS INFORMATION FRONT PANEL BUFFER FOR ADVANCED TV A front panel input provides easy access to an HDMI connector for connecting devices, such as an HD camcorder or video game console, to an HDTV. In designs where the main PCB is not near the side or front of the HDTV, a front panel HDMI input must be connected to the main board through a cable.
PAGE 16
AD8195 Data Sheet 5V 3.3V AMUXVCC 1µF HDMI CONNECTOR AMUXVCC TMDS ESD PROTECTION (OPTIONAL) IPA3 INA3 IPA2 INA2 IPA1 INA1 IPA0 INA0 AVCC, VTTI, VTTO OP3 ON3 OP2 ON2 OP1 ON1 OP0 AD8195 ON0 D2+ D2– D1+ D1– D0+ HDMI D0– RECEIVER CLK+ CLK– 3.3V OR 5V 2kΩ VREF_OUT 2kΩ 5V 1kΩ HPD DDC_SCL DDC_SDA CEC 47kΩ 2kΩ DDC_SCL DDC_SDA SCL_OUT SDA_OUT VREF_IN 47kΩ SCL_IN SDA_IN CEC_IN AMUXVCC 3kΩ COMP 10µF 0.01µF TMDS EDID EEPROM OPTIONAL EDID PLACEMENT 0.
PAGE 17
Data Sheet AD8195 TMDS Signals In the HDMI/DVI standard, four differential pairs carry the TMDS signals. In DVI, three of these pairs are dedicated to carrying RGB video and sync data. For HDMI, audio data is also interleaved with the video data; the DVI standard does not incorporate audio information. The fourth high speed differential pair is used for the AV data-word clock and runs at one-tenth the speed of the TMDS data channels. The four high speed channels of the AD8195 are identical.
PAGE 18
AD8195 Data Sheet TMDS Terminations 3W The AD8195 provides internal 50 Ω single-ended terminations for all of its high speed inputs and outputs. It is not necessary to include external termination resistors for the TMDS differential pairs on the PCB. W 3W SILKSCREEN LAYER 1: MICROSTRIP PCB DIELECTRIC LAYER 2: REFERENCE PLANE The output termination resistors of the AD8195 back terminate the output TMDS transmission lines.
PAGE 19
Data Sheet AD8195 OUTLINE DIMENSIONS 6.10 6.00 SQ 5.90 0.60 MAX 0.60 MAX PIN 1 INDICATOR 31 30 0.50 BSC 10 21 20 TOP VIEW 1.00 0.85 0.80 12° MAX SEATING PLANE 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.30 0.23 0.18 4.25 4.10 SQ 3.95 EXPOSED PAD (BOTTOM VIEW) 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 11 0.20 MIN 4.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 20
AD8195 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07049-0-8/12(B) Rev.