Datasheet

AD8194
Rev. 0 | Page 3 of 16
SPECIFICATIONS
T
A
= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2
7
− 1,
data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
Table 1.
Parameter Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel NRZ 2.25 Gbps
Bit Error Rate (BER) 10
−9
Added Deterministic Jitter 10 ps (p-p)
Added Random Jitter 1 ps (rms)
Differential Intrapair Skew At output 1 ps
Differential Interpair Skew
1
At output 30 ps
EQUALIZATION PERFORMANCE
Receiver Boost frequency = 1.125 GHz 12 dB
INPUT CHARACTERISTICS
Input Voltage Swing Differential 150 1200 mV
Input Common-Mode Voltage (V
ICM
) AVCC − 800 AVCC mV
OUTPUT CHARACTERISTICS
High Voltage Level Single-ended high speed channel AVCC mV
Low Voltage Level Single-ended high speed channel AVCC − 600 AVCC − 400 mV
Rise/Fall Time (20% to 80%) 75 178 ps
TERMINATION
Input Resistance Single-ended 50 Ω
Output Resistance Single-ended 50 Ω
POWER SUPPLY
AVCC Operating range 3 3.3 3.6 V
QUIESCENT CURRENT
2
AVCC 50 70 mA
VTTI 40 54 mA
VTTO 40 65 mA
POWER DISSIPATION
3
429 mW
SOURCE SELECT INTERFACE
Input High Voltage (V
IH
) S_SEL 2 V
Input Low Voltage (V
IL
) S_SEL 0.8 V
1
Differential interpair skew is measured between the TMDS pairs of a single link.
2
Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI link is deactivated. Minimum and
maximum limits are measured at the respective extremes of input termination resistance and input voltage swing.
3
The total power dissipation excludes power dissipated in the 50 Ω off-chip loads.