Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches LFCSP-32-VQ

Buffered 2:1 TMDS Switch

with Equalization

AD8194

Rev. 0

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FEATURES

2 inputs, 1 output HDMI/DVI high speed signal switch

Pin-to-pin compatible with the AD8193

Enables HDMI 1.3-compliant receiver

4 TMDS channels per input/output

Supports 250 Mbps to 2.25 Gbps data rates

Supports 25 MHz to 225 MHz pixel clocks

Fully buffered unidirectional inputs/outputs

Equalized inputs for operation with long HDMI cables

(20 m at 2.25 Gbps)

Matched 50 Ω input and output on-chip terminations

Low added jitter

Single-supply operation (3.3 V)

Standards compliant: HDMI receiver, DVI

32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP

APPLICATIONS

Advanced television (HDTV) sets

Multiple input displays

Projectors

A/V receivers

Set-top boxes

FUNCTIONAL BLOCK DIAGRAM

07004-001

AD8194

CONTROL

LOGIC

–

SWITCH

CORE

HIGH SPEED BUFFERED

VTTO

VTTI

IP_A[3:0]

IN_A[3:0]

IP_B[3:0]

IN_B[3:0]

VTTI

S_SEL

OP[3:0]

ON[3:0]

Figure 1.

TYPICAL APPLICATION

HDMI

RECEIVER

AD8194

HDTV SET

DVD PLAYER

SET-TOP BOX

07004-002

Figure 2. Typical AD8194 Application for HDTV Sets

GENERAL DESCRIPTION

The AD8194 is a low cost quad 2:1 TMDS® switch for high

speed HDMI™/DVI video applications. The AD8194 features

equalized inputs, ideal for systems with long cable runs. Its

primary function is to switch the high speed signals from one

of two single-link (HDMI or DVI) sources to the single-link

output. The AD8194 is a fully buffered switch solution with 50 Ω

input and output terminations, providing full-swing output

signal recovery and minimizing reflections for improved system

signal integrity.

The AD8194 is provided in a space-saving, 32-lead, LFCSP,

surface-mount, RoHS-compliant, plastic package and is specified

to operate over the −40°C to +85°C temperature range.

PRODUCT HIGHLIGHTS

1. Data supports rates up to 2.25 Gbps, enabling greater than

1080p deep color (12-bit color) HDMI formats and greater

than UXGA (1600 × 2300) DVI resolutions.

2. Fully buffered inputs and outputs.

3. Input cable equalizer enables use of long cables at the

input. For a typical 24 AWG cable, the AD8194 compen-

sates for more than 20 m at data rates up to 2.25 Gbps.

4. Matched 50 Ω on-chip input and output terminations

improve system signal integrity.

5. Single-pin source select bit.

6. Low added jitter.

Summary of content (16 pages)

PAGE 1
Buffered 2:1 TMDS Switch with Equalization AD8194 FEATURES FUNCTIONAL BLOCK DIAGRAM AVCC CONTROL LOGIC S_SEL VTTI IP_A[3:0] IN_A[3:0] + AD8194 VTTO 4 4 – SWITCH CORE EQ IP_B[3:0] IN_B[3:0] AVEE + – 4 Tx 4 4 + – OP[3:0] ON[3:0] 4 BUFFERED 07004-001 HIGH SPEED VTTI Figure 1.
PAGE 2
AD8194 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Applications....................................................................................... 1 Theory of Operation .........................................................................9 Functional Block Diagram ..............................................................
PAGE 3
AD8194 SPECIFICATIONS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. Table 1.
PAGE 4
AD8194 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter AVCC to AVEE VTTI VTTO Internal Power Dissipation High Speed Input Voltage High Speed Differential Input Voltage Source Select (S_SEL) Storage Temperature Range Operating Temperature Range Junction Temperature Rating 3.7 V AVCC + 0.6 V AVCC + 0.6 V 1.2 W AVCC − 1.4 V < VIN < AVCC + 0.6 V 2.0 V AVEE − 0.3 V < VIN < AVCC + 0.
PAGE 5
AD8194 27 AVEE 26 IP_B3 25 IN_B3 PIN 1 INDICATOR VTTI 3 24 IP_B2 23 IN_B2 22 AVCC AD8194 IN_A3 4 IP_A3 5 21 IP_B1 20 IN_B1 TOP VIEW (Not to Scale) AVCC 6 19 VTTI ON0 16 ON1 13 VTTO 14 OP0 15 AVEE 11 OP1 12 OP2 9 18 IP_B0 17 IN_B0 ON2 10 OP3 7 ON3 8 NOTES 1. THE AD8194 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE, WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE TO MEET THERMAL SPECIFICATIONS.
PAGE 6
AD8194 TYPICAL PERFORMANCE CHARACTERISTICS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. HDMI CABLE AD8194 DIGITAL PATTERN GENERATOR SERIAL DATA ANALYZER EVALUATION BOARD REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07004-004 SMA COAX CABLE 07004-007 250mV/DIV 07004-005 250mV/DIV Figure 4.
PAGE 7
AD8194 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. 0.6 0.5 40 0.4 JITTER (ps) 0.3 1080p 12-BIT 30 1080p 8-BIT 20 0.2 0 5 10 15 20 25 HDMI CABLE LENGTH (Meters) 0 07004-028 0 1080i/720p 480p 0 1080p 12-BIT 1080i/720p 480i DJ (p-p) RJ (rms) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.
PAGE 8
AD8194 50 40 40 30 30 20 10 10 DJ (p-p) RJ (rms) 2.7 2.9 3.1 3.3 3.5 3.7 INPUT COMMON-MODE VOLTAGE (V) 0 –40 DJ (p-p) RJ (rms) –15 60 60 85 160 58 RISE/FALL TIME 20% TO 80% (ps) 140 56 54 52 50 48 46 44 RISE TIME FALL TIME 120 100 80 60 40 20 42 –15 10 35 60 85 TEMPERATURE (°C) 0 –40 07004-035 SINGLE-ENDED INPUT RESISTANCE (Ω) 35 Figure 17. Jitter vs. Temperature Figure 15. Jitter vs.
PAGE 9
AD8194 THEORY OF OPERATION The AD8194 is an equalized, buffered TMDS switch with low added jitter. The output pins are electrically isolated from the inputs and the input equalizer recovers and transmits an open, full-swing data eye at the output, even for heavily attenuated input signals. The input equalizer of the AD8194 provides 12 dB of high frequency boost.
PAGE 10
AD8194 SWITCHING MODE Table 5. S_SEL Description The source selector pin, S_SEL, is used to select which of the two input groups is routed to the output. Source A is selected when S_SEL is pulled up to logic high, and Source B is selected when S_SEL is pulled down to logic low. Logic levels for this pin are set in accordance with the specifications listed in Table 5. The AD8194 can be used as a single-link TMDS buffer by setting S_SEL to one fixed logic value.
PAGE 11
AD8194 APPLICATION NOTES SWITCHING HIGH SPEED SIGNALS TMDS Signals The AD8194 is a quad 2:1 TMDS switch that is used to switch the high speed signals of two input HDMI links to a single HDMI output. The audiovisual (AV) data carried on these high speed channels is encoded by a technique called Transition Minimized Differential Signaling (TMDS) and, in the case of HDMI, is also encrypted according to the high bandwidth digital content protection (HDCP) standard.
PAGE 12
AD8194 Any group of four TMDS channels (Input A, Input B, or the output) should have closely matched trace lengths to minimize interpair skew. Severe interpair skew can cause the data on the four different channels of a group to arrive out of alignment with one another. A good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on FR4 material. The length of the TMDS traces should be minimized to reduce overall signal degradation.
PAGE 13
AD8194 Auxiliary Control Signals There are four single-ended control signals associated with each source or sink in an HDMI/DVI application. These are hot plug detect (HPD), consumer electronics control (CEC), and two display data channel (DDC) lines. The two signals on the DDC bus are SDA and SCL (serial data and serial clock, respectively). The AD8194, which is a low cost part, does not have any additional capability to switch these signals; other means are required to switch these signals if required.
PAGE 14
AD8194 Evaluation Board HDMI cables. However, this arrangement requires crossing over the TMDS signals on the output side (see Figure 24). The AD8194 evaluation board illustrates one way to implement a 2:1 HDMI link switch with an AD8194 and a CMOS switch. The AD8194 evaluation board deviates from a typical application in that it uses an HDMI connector for the output as well as for the inputs.
PAGE 15
AD8194 The low speed switching is performed by an MC74LVX4053. This part contributes a maximum on resistance of 108 Ω and a maximum capacitive load of 10 pF. The same select signal (S_SEL) controls both the AD8194 and the MC74LVX4053. 07004-015 Figure 26 shows the layout of the TMDS traces. These are 100 Ω differential, controlled-impedance traces. Serpentine traces are used for some of the paths to match the lengths within a group of four.
PAGE 16
AD8194 OUTLINE DIMENSIONS 5.00 BSC SQ PIN 1 INDICATOR TOP VIEW 0.60 MAX 0.60 MAX 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX SEATING PLANE 25 24 32 1 2.85 2.70 SQ 2.55 *EXPOSED PAD (BOT TOM VIEW) 17 16 PIN 1 INDICATOR 9 8 0.20 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.25 0.18 0.20 REF COPLANARITY 0.