Datasheet

AD8192
Rev. 0 | Page 9 of 28
T
A
= 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2
7
− 1,
data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
REFERENCE EYE DIAGRAM AT TP1
DIGITAL
PATTERN
GENERATOR
SMA COAX CABLE
HDMI CABLE
TP1 TP2 TP3
AD8192
EVALUATION
BOARD
SERIAL DATA
ANALYZER
07050-009
Figure 9. Test Circuit Diagram for Tx Eye Diagrams
07050-010
0.125UI/DIV AT 2.25Gbps
250mV/DI
V
Figure 10. Tx Eye Diagram at TP2, PE = 0 dB
07050-011
0.125UI/DIV AT 2.25Gbps
250mV/DI
V
Figure 11. Tx Eye Diagram at TP2, PE = 6 dB
07050-012
0.125UI/DIV AT 2.25Gbps
250mV/DI
V
Figure 12. Tx Eye Diagram at TP3, PE = 0 dB (Cable = 2 m, 24 AWG)
07050-013
0.125UI/DIV AT 2.25Gbps
250mV/DI
V
Figure 13. Tx Eye Diagram at TP3, PE = 6 dB (Cable = 10 m, 24 AWG)