Datasheet

AD8192
Rev. 0 | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
AVCC
2 IN
_
A0
3 IP
_
A0
4 AVEE
5 IN
_
A1
6 IP
_
A1
7 VTTI
8 IN
_
A2
9 IP
_
A2
10 AVCC
11 IN
_
A3
12 IP
_
A3
13 AVEE
14 I2C
_
ADDR
35 IP
_
B1
36 VTTI
37 IN
_
B2
38 IP
_
B2
39 AVEE
40 IN
_
B3
41 IP
_
B3
42 AVCC
34 IN
_
B1
33 AVCC
32 IP
_
B0
31 IN
_
B0
30 AVEE
29 I2C
_
SDA
15
DVCC
16
ON0
17
OP0
19
ON1
21
DVCC
20
OP1
22
ON2
23
OP2
24
VTTO
25
ON3
26
OP3
27
RESET
28
I2
C
_
SCL
18
VTTO
45
DDC_B0
46
CEC_O/I
47
AMUXVCC
48
VREF_COM
49
DDC_COM
1
50
DDC_COM0
51
VREF_AB
52
DVEE
53
CEC_I/O
54
H
PD_A
44
DDC_B1
43
HPD_B
TOP VIEW
(Not to Scale)
AD8192
55
DDC_A1
56
DDC_A
0
NOTES
1. THE AD8192 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE
OF THE PACKAGE WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO
MEET THERMAL SPECIFICATIONS.
07050-003
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1, 10, 33, 42 AVCC Power Positive Analog Supply. 3.3 V nominal.
2 IN_A0 HS I/O High Speed Input Complement.
3 IP_A0 HS I/O High Speed Input.
4, 13, 30, 39, ePAD AVEE Power Negative Analog Supply. 0 V nominal.
5 IN_A1 HS I/O High Speed Input Complement.
6 IP_A1 HS I/O High Speed Input.
7, 36 VTTI Power Input Termination Supply. Nominally connected to AVCC.
8 IN_A2 HS I/O High Speed Input Complement.
9 IP_A2 HS I/O High Speed Input.
11 IN_A3 HS I/O High Speed Input Complement.
12 IP_A3 HS I/O High Speed Input.
14 I2C_ADDR Control I
2
C Address LSB.
15, 21 DVCC Power Positive Digital Power Supply. 3.3 V nominal.
16 ON0 HS I/O High Speed Output Complement.
17 OP0 HS I/O High Speed Output.
18, 24 VTTO Power Output Termination Supply. Nominally connected to AVCC.
19 ON1 HS I/O High Speed Output Complement.
20 OP1 HS I/O High Speed Output.
22 ON2 HS I/O High Speed Output Complement.
23 OP2 HS I/O High Speed Output.
25 ON3 HS I/O High Speed Output Complement.
26 OP3 HS I/O High Speed Output.
27
RESET
Control Configuration Registers Reset. Normally pulled to AVCC.
28 I2C_SCL Control I
2
C Clock.
29 I2C_SDA Control I
2
C Data.
31 IN_B0 HS I/O High Speed Input Complement.
32 IP_B0 HS I/O High Speed Input.
34 IN_B1 HS I/O High Speed Input Complement.
35 IP_B1 HS I/O High Speed Input.