Datasheet

AD8192
Rev. 0 | Page 19 of 28
TRANSMITTER SETTINGS REGISTER
TX_PE[x]: High Speed (TMDS) Output Pre-Emphasis Level
Select Bus (For All TMDS Channels)
Table 20. TX_PE[x] Description
TX_PE[x] Description
00b No pre-emphasis (0 dB)
01b Low pre-emphasis (2 dB)
10b Medium pre-emphasis (4 dB)
11b High pre-emphasis (6 dB)
TX_PTO: High Speed (TMDS) Output Termination On/Off
Select Bit (For All Channels)
Table 21. TX_PTO Description
TX_PTO Description
0b Output termination off
1b Output termination on
TX_OCL: High Speed (TMDS) Output Current Level Select
Bit (For All Channels)
Table 22. TX_OCL Description
TX_OCL Description
0b Output current set to 10 mA
1b Output current set to 20 mA
SOURCE SIGN CONTROL REGISTER
A_SG[x]: High Speed (TMDS) Input A, Channel x Sign
Select Bits
Defines the input/input complement polarity of the Channel x.
Table 23. A_SG[x] Description
A_SG[x] Description
0b Channel sign is positive
1b Channel sign is inverted
Table 24. A_SG[x] Mapping
A_SG[x] OP[x] ON[x]
0b IP_A[x] IN_A[x]
1b IN_A[x] IP_A[x]
B_SG[x]: High Speed (TMDS) Input B, Channel x Sign
Select Bits
These bits define the input/input complement polarity of the
Channel x.
Table 25. B_SG[x] Description
B_SG[x] Description
0b Channel sign is positive
1b Channel sign is inverted
Table 26. B_SG[x] Mapping
B_SG[x] OP[x] ON[x]
0b IP_B[x] IN_B[x]
1b IN_B[x] IP_B[x]
SOURCE A INPUT/OUTPUT MAPPING REGISTER
A[x]_HS_MAP[1:0]: High Speed (TMDS) Input A, Output
Channel x, Select Bits
These bits define the input/output mapping of the high speed
channels when Source A is selected.
Table 27. A[x]_HS_MAP[1:0] Mapping
A[x]_HS_MAP[1:0] O[x]
00b A0
01b A1
10b A2
11b A3
SOURCE B INPUT/OUTPUT MAPPING REGISTER
B[x]_HS_MAP[1:0]: High speed (TMDS) Input B, Output
Channel x, Select Bits
These bits define the input/output mapping of the high speed
channels when Source B is selected.
Table 28. B[x]_HS_MAP[1:0] Mapping
B[x]_HS_MAP[1:0] O[x]
00b B0
01b B1
10b B2
11b B3