Datasheet
AD8192
Rev. 0 | Page 18 of 28
HIGH SPEED DEVICE MODES REGISTER
HS_EN: High Speed (TMDS) Switch Enable Bit
Table 10. HS_EN Description
HS_EN Description
0b High speed channels off, low power/standby mode
1b High speed channel on
HS_CH: High Speed (TMDS) Source Select Bit
Table 11. HS_CH Mapping
HS_CH O[3:0] Description
0b A[3:0] High Speed Source A switched to output
1b B[3:0] High Speed Source B switched to output
AUXILIARY DEVICE MODES REGISTER
AUX_LK: Auxiliary (Low Speed) Switch Mode Lock Bit
Table 12. AUX_LK Description
AUX_LK Description
0b
Auxiliary switch lock off, auxiliary source is switched
independently of the high speed source
1b
Auxiliary switch lock on, auxiliary switch source select
is slaved to the high speed switch source select bit
AUX_EN: Auxiliary (Low Speed) Switch Enable Bit
Table 13. AUX_EN Description
AUX_EN Description
0b
Auxiliary switch off, no low speed input/output to
low speed common input/output connection
1b Auxiliary switch on
AUX_CH: Auxiliary (Low Speed) Switch Source Select Bit
Table 14. AUX_CH Mapping
AUX_CH AUX_COM[3:0] Description
0b AUX_A[3:0]
Auxiliary Source A switched to
output
1b AUX_B[3:0]
Auxiliary Source B switched to
output
RECEIVER SETTINGS REGISTER
RX_TO: High Speed (TMDS) Input Termination Mode
Control Select Bit
Table 15. RX_TO Description
RX_TO Description
0b
Input termination mode is manual, individual
terminations can be enabled/disabled according to
settings in the input termination pulse register
1b
Input termination for TMDS Channel x is always
connected
INPUT TERMINATION CONTROL REGISTER
RX_PT[x]: High Speed (TMDS) Input Termination x,
Select Bit
Table 16. RX_PT[x] Description
RX_PT[x] Description
0b
Input termination mode for TMDS Channel x is
always disconnected
1b
Input termination for TMDS Channel x is always
connected
Table 17. RX_PT[x] Mapping
RX_PT[x] Corresponding Input TMDS Channel
Bit 0 A0
Bit 1 A1
Bit 2 A2
Bit 3 A3
Bit 4 B3
Bit 5 B2
Bit 6 B1
Bit 7 B0
RECEIVE EQUALIZER REGISTER
RX_EQ[x]: High Speed (TMDS) Input x, Equalization Level
Select Bit
Table 18. RX_EQ[x] Description
RX_EQ[x] Description
0b Low equalization (6 dB)
1b High equalization (12 dB)
Table 19. RX_EQ[x] Mapping
RX_EQ[x] Corresponding Input TMDS Channel
Bit 0 A0
Bit 1 A1
Bit 2 A2
Bit 3 A3
Bit 4 B3
Bit 5 B2
Bit 6 B1
Bit 7 B0