Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - multiplexers TSSOP 24

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AD8183/AD8185

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1999

380 MHz, 25 mA,

Triple 2:1 Multiplexers

FEATURES

Fully Buffered Inputs and Outputs

Fast Channel-to-Channel Switching: 15 ns

High Speed

380 MHz Bandwidth (–3 dB) 200 mV p-p

310 MHz Bandwidth (–3 dB) 2 V p-p

1000 V/␮s Slew Rate G = +1, 2 V Step

1150 V/␮s Slew Rate G = +2, 2 V Step

Fast Settling Time of 15 ns to 0.1%

Low Power: 25 mA

Excellent Video Specifications (R

= 150 ⍀)

Gain Flatness of 0.1 dB to 90 MHz

0.01% Differential Gain Error

0.02ⴗ Differential Phase Error

Low All-Hostile Crosstalk –84 dB @ 5 MHz

–54 dB @ 50 MHz

Low Channel-to-Channel Crosstalk –56 dB @ 100 MHz

High “OFF” Isolation of –100 dB @ 10 MHz

Low Cost

Fast High Impedance Output Disable Feature for

Connecting Multiple Devices

APPLICATIONS

Pixel Switching for “Picture-In-Picture”

Switching RGB in LCD and Plasma Displays

RGB Video Switchers and Routers

PRODUCT DESCRIPTION

The AD8183 (G = +1) and AD8185 (G = +2) are high speed

triple 2:1 multiplexers. They offer –3 dB signal bandwidth up to

380 MHz, along with slew rate of 1000 V/µs. With better than

–90 dB of channel-to-channel crosstalk and isolation at 10 MHz,

they are useful in many high-speed applications. The differential

gain and differential phase errors of 0.01% and 0.02° respectively,

along with 0.1 dB flatness to 90 MHz make the AD8183 and

AD8185 ideal for professional video and RGB multiplexing. They

offer 15 ns channel-to-channel switching time, making them

an excellent choice for switching video signals, while consuming

less than 25 mA on ±5 V supply voltages.

Both devices offer a high speed disable feature that can set the

output into a high impedance state. This allows the building of

larger input arrays while minimizing “OFF” channel output

loading. They operate on voltage supplies of ±5 V and are offered

in a 24-lead TSSOP package.

Table I. Truth Table

SEL A/B OE OUT

0 0 INA

1 0 INB

0 1 High Z

1 1 High Z

200mV

2ns

= 1.4V STEP

= 150V

1.4V

1.2V

1.0V

0.8V

0.6V

0.4V

0.2V

0.0V

Figure 1. AD8185 Pulse Response; R

= 150

Ω

FUNCTIONAL BLOCK DIAGRAM

AD8183/AD8185

IN0B

GND

IN1B

GND

IN2B

IN0A

DGND

IN1A

GND

IN2A

DVCC

OUT2

SEL A/B

OUT1

OUT0

SELECT

DISABLE

Summary of content (16 pages)

PAGE 1
a FEATURES Fully Buffered Inputs and Outputs Fast Channel-to-Channel Switching: 15 ns High Speed 380 MHz Bandwidth (–3 dB) 200 mV p-p 310 MHz Bandwidth (–3 dB) 2 V p-p 1000 V/␮s Slew Rate G = +1, 2 V Step 1150 V/␮s Slew Rate G = +2, 2 V Step Fast Settling Time of 15 ns to 0.1% Low Power: 25 mA Excellent Video Specifications (RL = 150 ⍀) Gain Flatness of 0.1 dB to 90 MHz 0.01% Differential Gain Error 0.
PAGE 2
AD8183/AD8185–SPECIFICATIONS (T = 25ⴗC, V = ⴞ5 V, R = 1 k⍀ unless otherwise noted) A Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth (Small Signal) –3 dB Bandwidth (Small Signal) –3 dB Bandwidth (Large Signal) –3 dB Bandwidth (Large Si 0.1 dB Bandwidth Slew Rate Settling Time to 0.
PAGE 3
AD8183/AD8185 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 V DVCC to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.2 V Internal Power Dissipation2, 3 AD8183/AD8185 24-Lead TSSOP (RU) . . . . . . . . . . . . . 1 W Input Voltage IN0A, IN0B, IN1A, IN1B, IN2A, IN2B . . . . . VEE ≤ VIN ≤ V CC SELECT A/B, OE . . . . . . . . . . . . . . . . . . DGND ≤ VIN ≤ VCC Output Short Circuit Duration . . . . . . . . . . . . . .
PAGE 4
AD8183/AD8185 1 1 GAIN GAIN 0 200mV p-p –1 –3 0 –4 –0.1 –0.2 –5 200mV p-p 2V p-p VO AS SHOWN RL = 150V –0.3 –7 –0.4 –8 –9 0.1 1 10 FREQUENCY – MHz 100 1k 0 0 –4 –0.1 –0.2 –5 –6 VO AS SHOWN RL = 150V –8 –0.5 –0.6 –9 0.1 1 10 FREQUENCY – MHz 2 200mV p-p 0.3 1 GAIN 0.2 –2 0.1 0 –4 –0.1 –0.2 2V p-p –0.3 FLATNESS – dB GAIN – dB FLATNESS –3 200mV p-p 2V p-p 0.1 –1 FLATNESS 0 –2 –3 –0.1 200mV p-p 2V p-p –0.2 –4 –5 VO AS SHOWN RL = 1kV –0.3 –7 –0.4 –6 –0.
PAGE 5
AD8183/AD8185 –10 –10 RL = 1kV RT = 37.5V –30 –30 –40 –40 –50 ALL-HOSTILE –60 ADJACENT –70 –90 –100 –100 10 100 FREQUENCY – MHz 1 –110 1k ADJACENT CHANNEL-TO-CHANNEL CROSSTALK – dB –40 –50 –60 DRIVE B, LISTEN A –70 –80 DRIVE A, LISTEN B –90 –100 10 100 FREQUENCY – MHz 1 RL = 150V RT = 37.5V RTI MEASURED –20 –30 –40 –50 –60 DRIVE A, LISTEN B –70 –80 DRIVE B, LISTEN A –90 –100 –110 1k Figure 10. AD8183 Channel-to-Channel Crosstalk vs. Frequency 10 100 FREQUENCY – MHz 1 1k Figure 13.
PAGE 6
0 1M 1M 1M INPUT IMPEDANCE – V INPUT IMPEDANCE – V AD8183/AD8185 100k 10k 1k 100k 1k 100 100 0.1 10k 1 10 FREQUENCY – MHz 100 0.1 1k 1 10 FREQUENCY – MHz 100 1k Figure 18. AD8185 Input Impedance vs. Frequency Figure 15. AD8183 Input Impedance vs. Frequency 1k 1k 100 OUTPUT IMPEDANCE – V OUTPUT IMPEDANCE – V 1k 10 1 0.1 0.1 10 1 0.1 1 10 FREQUENCY – MHz 100 0.1 1k 1M 100k 100k OUTPUT IMPEDANCE – V 1M 10k 1k 100 10 0.
PAGE 7
–40 –40 –50 –50 –60 –60 –70 –70 OFF ISOLATION – dB OFF ISOLATION – dB AD8183/AD8185 –80 –90 –100 –110 –80 –90 –100 –110 –120 –120 –130 –130 –140 0.1 1 10 FREQUENCY – MHz 100 –140 0.1 500 10 FREQUENCY – MHz 100 500 Figure 24. AD8185 Off Isolation, Input–Output Figure 21. AD8183 Off Isolation, Input–Output –10 0 0 10 10 20 20 PSRR – dB –10 PSRR – dB 1 30 –PSRR 40 –PSRR 30 40 +PSRR 50 50 +PSRR 60 60 70 70 80 0.1 1 10 FREQUENCY – MHz 80 0.
PAGE 8
AD8183/AD8185 VO = 2V STEP RL = 150V 0.1%/DIV 0.1%/DIV VO = 2V STEP RL = 150V 0 5 10 15 20 25 30 5ns/DIV 0 35 40 10 15 20 25 30 5ns/DIV 35 40 Figure 30. AD8185 0.1% Settling Time Figure 27. AD8183 0.1% Settling Time +1.8V 100 +1.8V 100 5 90 90 SEL A/B SEL A/B +1.0V +1.0V IN0A AT +0.5V IN0A AT +1V +1.0V +1.0V V OUT V OUT 10 0% 10 0V IN0B AT –1V 0% 0V IN0B AT –0.5V –1.0V –1.0V 10ns 10ns Figure 31. AD8185 Channel-to-Channel Switching Time Figure 28.
PAGE 9
AD8183/AD8185 VO = 200mV STEP 0.1V R = 150V L VO = 200mV STEP 0.10V R = 1kV L 0.05V 0.05V 0.0V 0.0V –0.05V –0.05V –0.10V –0.1V 25mV 2ns VO = 0.7V STEP 0.7V R = 1kV L VO = 1.4V STEP 1.4V R = 150V L 0.6V 1.2V 0.5V 1.0V 0.4V 0.8V 0.3V 0.6V 0.2V 0.4V 0.1V 0.2V 0.0V 0.0V 100mV 200mV 2ns 2ns Figure 37. AD8185 Video Amplitude Pulse Response; RL = 150 Ω Figure 34. AD8183 Video Amplitude Pulse Response; RL = 1 kΩ VO = 2V STEP 1.0V R = 1kV L VO = 2V STEP 1.0V R = 150V L 0.5V 0.
PAGE 10
AD8183/AD8185 THEORY OF OPERATION The AD8183 (G = +1) and AD8185 (G = +2) are triple-output, 2:1 multiplexers with TTL-compatible global input switching and output enable control. Optimized for selecting between two RGB (red, green, blue) video sources, the devices have high peak slew rates, maintaining their bandwidth for large signals. Additionally, the multiplexers are compensated for high phase margin, minimizing overshoot for good pixel resolution.
PAGE 11
AD8183/AD8185 Third, the additional power and ground pins also yield lower impedance on the power and ground lines, and therefore minimize the effects of shared impedances on crosstalk. A delay circuit is provided for each device to ensure that the outputs of one device are disabled before the outputs of the other are enabled. Signal routing is also important for keeping crosstalk low. Shielding and separation should be used for signals that must run parallel over some length on the PC board.
PAGE 12
AD8183/AD8185 result, the input and output traces, in addition to having a controlled impedance, are well shielded. 41 for the arrangement of the PCB layers. If J10 is used, the user may wish to install a 50 Ω termination resistor at R10. OE (Pin 23 of the device) allows the three outputs to be enabled or disabled. When OE is at logic low, (equal to or less than 0.8 V), Outputs 0, 1, and 2 are enabled. When OE is at logic high, (equal to or greater than 2.
PAGE 13
AD8183/AD8185 Figure 43. Component Side Silkscreen Figure 44. Board Layout (Component Side) REV.
PAGE 14
AD8183/AD8185 Figure 45. Board Layout (75 Ω Signal Layer) Figure 46. Board Layout (Ground Plane) –14– REV.
PAGE 15
AD8183/AD8185 Figure 47. Board Layout (Circuit Side;) 50 Ω Signal Layer Figure 48. Circuit Side Silkscreen REV.
PAGE 16
AD8183/AD8185 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic TSSOP (RU-24) 24 C3689–5–10/99 0.311 (7.90) 0.303 (7.70) 13 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 12 PIN 1 SEATING PLANE 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 88 08 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. 0.006 (0.15) 0.002 (0.05) –16– REV.