Datasheet

AD8175 Data Sheet
Rev. B | Page 6 of 40
TIMING CHARACTERISTICS (PARALLEL MODE)
Specifications subject to change without notice.
Table 7.
Limit
Parameter Symbol Min Typ Max Unit
Parallel Data Setup Time t
1
80 ns
WE
Pulse Width t
2
110 ns
Parallel Hold Time t
3
150 ns
WE
Pulse Separation t
4
90 ns
WE
to
UPDATE
Delay t
5
10 ns
UPDATE
Pulse Width t
6
90 ns
Propagation Delay,
UPDATE
to Switch On
80
ns
RST
Time 140 200 ns
t
2
t
4
1
0
WE
1
0
t
1
t
3
1 = LATCHED
0 = TRANSPARENT
UPDATE
t
6
D0 TO D4
A0 TO A4
t
5
06478-003
Figure 3. Timing Diagram, Parallel Mode
Table 8. Logic Levels, V
DD
= 3.3 V
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
SER
/PAR,
WE
,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3,
UPDATE
SER
/PAR,
WE
,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3,
UPDATE
SEROUT SEROUT
SER
/PAR,
WE
,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3,
UPDATE
SER
/PAR,
WE
,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3,
UPDATE
SEROUT SEROUT
2.0 V min 0.6 V max Disabled Disabled 20 µA max −20 µA max Disabled Disabled
Table 9. H and V Logic Levels, V
DD
= 3.3 V
V
OH
V
OL
I
OH
I
OL
2.7 V min 0.5 V max –3 mA max 3 mA max
Table 10.
RST
Logic Levels, V
DD
= 3.3 V
V
IH
V
IL
I
IH
I
IL
2.0 V min 0.6 V max −60 µA max −120 µA max
Table 11.
CS
Logic Levels, V
DD
= 3.3 V
V
OH
V
OL
I
IH
I
OL
2.0 V min 0.6 V max 100 µA max 40 µA max